Andreas Hansson de34e49d15 MEM: Simplify ports by removing EventManager ...

This patch removes the inheritance of EventManager from the ports and
moves all responsibility for event queues to the owner. Eventually the
event manager should be the interface block, which could either be the
structural owner or a subblock like a LSQ in the O3 CPU for example.

2012-01-17 12:55:09 -06:00

..

cache

MEM: Simplify ports by removing EventManager

2012-01-17 12:55:09 -06:00

config

Fixes to get prefetching working again.

2009-02-16 08:56:40 -08:00

protocol

Ruby: Change the access permissions for MOESI hammer

2012-01-17 12:55:07 -06:00

ruby

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

slicc

Ruby: Add infrastructure for recording cache contents

2012-01-11 13:29:15 -06:00

bridge.cc

MEM: Simplify ports by removing EventManager

2012-01-17 12:55:09 -06:00

bridge.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

Bridge.py

DMA: Add IOCache and fix bus bridge to optionally only send requests one

2007-08-10 16:14:01 -04:00

bus.cc

mem: Change DPRINTF prints more useful destination port number.

2012-01-09 18:08:20 -06:00

bus.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

Bus.py

bus: clean up default responder code.

2010-08-17 05:06:21 -07:00

dram.cc

Replace curTick global variable with accessor functions.

2011-01-07 21:50:29 -08:00

dram.hh

stats: Fix all stats usages to deal with template fixes

2009-03-05 19:09:53 -08:00

fs_translating_port_proxy.cc

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

fs_translating_port_proxy.hh

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

mem_object.cc

params: Get rid of the remnants of the old style parameter configuration stuff.

2008-08-11 12:22:17 -07:00

mem_object.hh

params: Get rid of the remnants of the old style parameter configuration stuff.

2008-08-11 12:22:17 -07:00

MemObject.py

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

mport.cc

Replace curTick global variable with accessor functions.

2011-01-07 21:50:29 -08:00

mport.hh

Create a message port for sending messages as apposed to reading/writing a memory range.

2008-10-12 12:08:51 -07:00

packet_access.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

packet.cc

Packet: Put back part of the assert

2012-01-11 19:27:11 -05:00

packet.hh

Packet: Add derived class FunctionalPacket to enable partial functional reads

2012-01-09 18:10:05 -06:00

page_table.cc

gcc: fix unused variable warnings from GCC 4.6.1

2011-12-13 11:49:27 -08:00

page_table.hh

SE: move page allocation from PageTable to Process

2011-10-22 22:30:08 -07:00

physical.cc

physmem: Improved fatal message for size mismatch

2011-12-01 10:08:52 -08:00

physical.hh

SE: Fix simulating more than 4GB of RAM in SE mode

2010-11-19 18:01:01 -06:00

PhysicalMemory.py

Make default PhysicalMemory latency slightly more realistic.

2008-08-03 18:13:29 -04:00

port_proxy.hh

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

port.cc

MEM: Simplify ports by removing EventManager

2012-01-17 12:55:09 -06:00

port.hh

MEM: Simplify ports by removing EventManager

2012-01-17 12:55:09 -06:00

request.hh

Mem: Allow ASID to be set after request is created.

2011-09-13 12:06:13 -05:00

SConscript

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

se_translating_port_proxy.cc

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

se_translating_port_proxy.hh

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

tport.cc

MEM: Simplify ports by removing EventManager

2012-01-17 12:55:09 -06:00

tport.hh

MEM: Simplify ports by removing EventManager

2012-01-17 12:55:09 -06:00