f5858fe81f
The ROM field was originally intended as a future alternate way to load VBIOS without the ROM being on the disk image. This code path is never taken for the devices gem5 supports and there is no gem5 implementation. Deprecate the rom_binary field for this reason. Similarly, MMIO traces were only used for Vega10. Deprecate this as Vega10 is now deprecated. The MMIO trace reader is kept as it may still be useful in the future. It is still the primary way to handle devies which have graphics capability. None of the devices supported by gem5 have graphics now that Vega10 is deprecated.
145 lines
5.3 KiB
Python
145 lines
5.3 KiB
Python
# Copyright (c) 2021 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from this
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# software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.ClockedObject import ClockedObject
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from m5.objects.Device import (
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DmaDevice,
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DmaVirtDevice,
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)
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from m5.objects.PciDevice import (
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PciDevice,
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PciLegacyIoBar,
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PciMemBar,
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PciMemUpperBar,
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)
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from m5.params import *
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from m5.proxy import *
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# PCI device model for an AMD Vega 10 based GPU. The PCI codes and BARs
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# correspond to a Vega Frontier Edition hardware device. None of the PCI
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# related values in this class should be changed.
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#
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# This class requires a ROM binary and an MMIO trace to initialize the
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# device registers and memory. It is intended only to be used in full-system
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# simulation under Linux where the amdgpu driver is modprobed.
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class AMDGPUDevice(PciDevice):
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type = "AMDGPUDevice"
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cxx_header = "dev/amdgpu/amdgpu_device.hh"
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cxx_class = "gem5::AMDGPUDevice"
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# Human readable name for device ID
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device_name = Param.String("Vega10", "Codename for device")
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# IDs for AMD Vega 10
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VendorID = 0x1002
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DeviceID = 0x6863
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# Command 0x3 never gets sent indicating IO and Mem bars are enabled. Hard
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# code the command here and deal unassigned BARs on C++ side.
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Command = 0x3
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Status = 0x0280
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Revision = 0x0
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ClassCode = 0x03
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SubClassCode = 0x00
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ProgIF = 0x00
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# Use max possible BAR size for Vega 10. We can override with driver param
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BAR0 = PciMemBar(size="16GiB")
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BAR1 = PciMemUpperBar()
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BAR2 = PciMemBar(size="2MiB")
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BAR3 = PciMemUpperBar()
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BAR4 = PciLegacyIoBar(addr=0xF000, size="256B")
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BAR5 = PciMemBar(size="512KiB")
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InterruptLine = 14
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InterruptPin = 2
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ExpansionROM = 0
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checkpoint_before_mmios = Param.Bool(
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False, "Take a checkpoint before the device begins sending MMIOs"
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)
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# SDMA engines. There are a different number depending on device,
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# therefore an array is used.
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sdmas = VectorParam.SDMAEngine("All SDMA Engines")
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# The cp is needed here to handle certain packets the device may receive.
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# The config script should not create a new cp here but rather assign the
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# same cp that is assigned to the Shader SimObject.
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cp = Param.GPUCommandProcessor(NULL, "Command Processor")
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pm4_pkt_procs = VectorParam.PM4PacketProcessor("PM4 Packet Processor")
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memory_manager = Param.AMDGPUMemoryManager("GPU Memory Manager")
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memories = VectorParam.AbstractMemory([], "All memories in the device")
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device_ih = Param.AMDGPUInterruptHandler("GPU Interrupt handler")
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class SDMAEngine(DmaVirtDevice):
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type = "SDMAEngine"
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cxx_header = "dev/amdgpu/sdma_engine.hh"
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cxx_class = "gem5::SDMAEngine"
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mmio_base = Param.Addr(0x0, "Base MMIO Address")
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mmio_size = Param.Addr(0x800, "Size of MMIO range")
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gpu_device = Param.AMDGPUDevice(NULL, "GPU Controller")
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walker = Param.VegaPagetableWalker("Page table walker")
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class PM4PacketProcessor(DmaVirtDevice):
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type = "PM4PacketProcessor"
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cxx_header = "dev/amdgpu/pm4_packet_processor.hh"
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cxx_class = "gem5::PM4PacketProcessor"
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# Default to 0 as the common case is one PM4 packet processor
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ip_id = Param.Int(0, "Instance ID of this PM4 processor")
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mmio_range = Param.AddrRange("Range of MMIO addresses")
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class AMDGPUMemoryManager(ClockedObject):
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type = "AMDGPUMemoryManager"
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cxx_header = "dev/amdgpu/memory_manager.hh"
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cxx_class = "gem5::AMDGPUMemoryManager"
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cache_line_size = Param.UInt64("Cache line size in bytes")
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port = RequestPort("Memory Port to access VRAM (device memory)")
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system = Param.System(Parent.any, "System the dGPU belongs to")
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class AMDGPUInterruptHandler(DmaDevice):
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type = "AMDGPUInterruptHandler"
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cxx_header = "dev/amdgpu/interrupt_handler.hh"
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cxx_class = "gem5::AMDGPUInterruptHandler"
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class AMDGPUSystemHub(DmaDevice):
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type = "AMDGPUSystemHub"
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cxx_class = "gem5::AMDGPUSystemHub"
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cxx_header = "dev/amdgpu/system_hub.hh"
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