# Copyright (c) 2021 Advanced Micro Devices, Inc.
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from m5.objects.ClockedObject import ClockedObject
from m5.objects.Device import (
    DmaDevice,
    DmaVirtDevice,
)
from m5.objects.PciDevice import (
    PciDevice,
    PciLegacyIoBar,
    PciMemBar,
    PciMemUpperBar,
)
from m5.params import *
from m5.proxy import *


# PCI device model for an AMD Vega 10 based GPU. The PCI codes and BARs
# correspond to a Vega Frontier Edition hardware device. None of the PCI
# related values in this class should be changed.
#
# This class requires a ROM binary and an MMIO trace to initialize the
# device registers and memory. It is intended only to be used in full-system
# simulation under Linux where the amdgpu driver is modprobed.
class AMDGPUDevice(PciDevice):
    type = "AMDGPUDevice"
    cxx_header = "dev/amdgpu/amdgpu_device.hh"
    cxx_class = "gem5::AMDGPUDevice"

    # Human readable name for device ID
    device_name = Param.String("Vega10", "Codename for device")

    # IDs for AMD Vega 10
    VendorID = 0x1002
    DeviceID = 0x6863
    # Command 0x3 never gets sent indicating IO and Mem bars are enabled. Hard
    # code the command here and deal unassigned BARs on C++ side.
    Command = 0x3
    Status = 0x0280
    Revision = 0x0
    ClassCode = 0x03
    SubClassCode = 0x00
    ProgIF = 0x00

    # Use max possible BAR size for Vega 10. We can override with driver param
    BAR0 = PciMemBar(size="16GiB")
    BAR1 = PciMemUpperBar()
    BAR2 = PciMemBar(size="2MiB")
    BAR3 = PciMemUpperBar()
    BAR4 = PciLegacyIoBar(addr=0xF000, size="256B")
    BAR5 = PciMemBar(size="512KiB")

    InterruptLine = 14
    InterruptPin = 2
    ExpansionROM = 0

    checkpoint_before_mmios = Param.Bool(
        False, "Take a checkpoint before the device begins sending MMIOs"
    )

    # SDMA engines. There are a different number depending on device,
    # therefore an array is used.
    sdmas = VectorParam.SDMAEngine("All SDMA Engines")

    # The cp is needed here to handle certain packets the device may receive.
    # The config script should not create a new cp here but rather assign the
    # same cp that is assigned to the Shader SimObject.
    cp = Param.GPUCommandProcessor(NULL, "Command Processor")
    pm4_pkt_procs = VectorParam.PM4PacketProcessor("PM4 Packet Processor")
    memory_manager = Param.AMDGPUMemoryManager("GPU Memory Manager")
    memories = VectorParam.AbstractMemory([], "All memories in the device")
    device_ih = Param.AMDGPUInterruptHandler("GPU Interrupt handler")


class SDMAEngine(DmaVirtDevice):
    type = "SDMAEngine"
    cxx_header = "dev/amdgpu/sdma_engine.hh"
    cxx_class = "gem5::SDMAEngine"

    mmio_base = Param.Addr(0x0, "Base MMIO Address")
    mmio_size = Param.Addr(0x800, "Size of MMIO range")

    gpu_device = Param.AMDGPUDevice(NULL, "GPU Controller")
    walker = Param.VegaPagetableWalker("Page table walker")


class PM4PacketProcessor(DmaVirtDevice):
    type = "PM4PacketProcessor"
    cxx_header = "dev/amdgpu/pm4_packet_processor.hh"
    cxx_class = "gem5::PM4PacketProcessor"

    # Default to 0 as the common case is one PM4 packet processor
    ip_id = Param.Int(0, "Instance ID of this PM4 processor")
    mmio_range = Param.AddrRange("Range of MMIO addresses")


class AMDGPUMemoryManager(ClockedObject):
    type = "AMDGPUMemoryManager"
    cxx_header = "dev/amdgpu/memory_manager.hh"
    cxx_class = "gem5::AMDGPUMemoryManager"

    cache_line_size = Param.UInt64("Cache line size in bytes")

    port = RequestPort("Memory Port to access VRAM (device memory)")
    system = Param.System(Parent.any, "System the dGPU belongs to")


class AMDGPUInterruptHandler(DmaDevice):
    type = "AMDGPUInterruptHandler"
    cxx_header = "dev/amdgpu/interrupt_handler.hh"
    cxx_class = "gem5::AMDGPUInterruptHandler"


class AMDGPUSystemHub(DmaDevice):
    type = "AMDGPUSystemHub"
    cxx_class = "gem5::AMDGPUSystemHub"
    cxx_header = "dev/amdgpu/system_hub.hh"