a33f3d3967
Jazelle state has been officially removed in Armv8. Every AArch32 implementation must still support the "Trivial Jazelle implementation", which means that while the instruction set has been removed, it is still possible for privileged software to access some Jazelle registers like JIDR,JMCR, and JOSCR which are just treated as RAZ Change-Id: Ie403c4f004968eb4cb45fa51067178a550726c87 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
397 lines
9.6 KiB
C++
397 lines
9.6 KiB
C++
/*
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* Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ARM_PCSTATE_HH__
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#define __ARCH_ARM_PCSTATE_HH__
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#include "arch/generic/pcstate.hh"
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#include "base/bitunion.hh"
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#include "base/types.hh"
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#include "debug/Decoder.hh"
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namespace gem5
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{
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namespace ArmISA
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{
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BitUnion8(ITSTATE)
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/* Note that the split (cond, mask) below is not as in ARM ARM.
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* But it is more convenient for simulation. The condition
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* is always the concatenation of the top 3 bits and the next bit,
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* which applies when one of the bottom 4 bits is set.
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* Refer to predecoder.cc for the use case.
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*/
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Bitfield<7, 4> cond;
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Bitfield<3, 0> mask;
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// Bitfields for moving to/from CPSR
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Bitfield<7, 2> top6;
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Bitfield<1, 0> bottom2;
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EndBitUnion(ITSTATE)
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class PCState : public GenericISA::UPCState<4>
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{
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protected:
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typedef GenericISA::UPCState<4> Base;
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enum FlagBits
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{
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ThumbBit = (1 << 0),
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AArch64Bit = (1 << 2)
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};
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uint8_t flags = 0;
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uint8_t nextFlags = 0;
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uint8_t _itstate = 0;
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uint8_t _nextItstate = 0;
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uint8_t _size = 0;
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bool _illegalExec = false;
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// Software Step flags
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bool _debugStep = false;
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bool _stepped = false;
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public:
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void
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set(Addr val) override
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{
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Base::set(val);
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npc(val + (thumb() ? 2 : 4));
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}
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PCState(const PCState &other) : Base(other),
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flags(other.flags), nextFlags(other.nextFlags),
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_itstate(other._itstate), _nextItstate(other._nextItstate),
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_size(other._size), _illegalExec(other._illegalExec),
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_debugStep(other._debugStep), _stepped(other._stepped)
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{}
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PCState &operator=(const PCState &other) = default;
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PCState() {}
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explicit PCState(Addr val) { set(val); }
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PCStateBase *clone() const override { return new PCState(*this); }
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void
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update(const PCStateBase &other) override
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{
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Base::update(other);
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auto &pcstate = other.as<PCState>();
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flags = pcstate.flags;
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nextFlags = pcstate.nextFlags;
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_itstate = pcstate._itstate;
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_nextItstate = pcstate._nextItstate;
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_size = pcstate._size;
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_illegalExec = pcstate._illegalExec;
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_debugStep = pcstate._debugStep;
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_stepped = pcstate._stepped;
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}
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bool
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illegalExec() const
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{
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return _illegalExec;
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}
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void
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illegalExec(bool val)
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{
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_illegalExec = val;
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}
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bool
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debugStep() const
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{
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return _debugStep;
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}
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void
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debugStep(bool val)
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{
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_debugStep = val;
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}
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bool
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stepped() const
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{
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return _stepped;
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}
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void
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stepped(bool val)
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{
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_stepped = val;
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}
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bool
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thumb() const
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{
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return flags & ThumbBit;
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}
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void
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thumb(bool val)
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{
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if (val)
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flags |= ThumbBit;
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else
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flags &= ~ThumbBit;
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}
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bool
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nextThumb() const
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{
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return nextFlags & ThumbBit;
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}
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void
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nextThumb(bool val)
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{
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if (val)
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nextFlags |= ThumbBit;
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else
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nextFlags &= ~ThumbBit;
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}
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void size(uint8_t s) { _size = s; }
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uint8_t size() const { return _size; }
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bool
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branching() const override
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{
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return ((this->pc() + this->size()) != this->npc());
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}
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bool
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aarch64() const
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{
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return flags & AArch64Bit;
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}
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void
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aarch64(bool val)
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{
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if (val)
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flags |= AArch64Bit;
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else
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flags &= ~AArch64Bit;
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}
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bool
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nextAArch64() const
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{
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return nextFlags & AArch64Bit;
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}
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void
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nextAArch64(bool val)
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{
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if (val)
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nextFlags |= AArch64Bit;
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else
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nextFlags &= ~AArch64Bit;
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}
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uint8_t
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itstate() const
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{
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return _itstate;
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}
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void
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itstate(uint8_t value)
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{
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_itstate = value;
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}
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uint8_t
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nextItstate() const
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{
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return _nextItstate;
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}
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void
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nextItstate(uint8_t value)
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{
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_nextItstate = value;
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}
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void
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advance() override
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{
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Base::advance();
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flags = nextFlags;
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npc(pc() + (thumb() ? 2 : 4));
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if (_nextItstate) {
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_itstate = _nextItstate;
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_nextItstate = 0;
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} else if (_itstate) {
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ITSTATE it = _itstate;
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uint8_t cond_mask = it.mask;
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uint8_t thumb_cond = it.cond;
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DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n",
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thumb_cond, cond_mask);
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cond_mask <<= 1;
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uint8_t new_bit = bits(cond_mask, 4);
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cond_mask &= mask(4);
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if (cond_mask == 0)
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thumb_cond = 0;
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else
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replaceBits(thumb_cond, 0, new_bit);
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DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n",
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thumb_cond, cond_mask);
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it.mask = cond_mask;
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it.cond = thumb_cond;
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_itstate = it;
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}
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}
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void
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uEnd()
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{
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advance();
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upc(0);
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nupc(1);
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}
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Addr
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instPC() const
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{
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return pc() + (thumb() ? 4 : 8);
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}
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void
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instNPC(Addr val)
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{
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// @todo: review this when AArch32/64 interprocessing is
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// supported
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if (aarch64())
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npc(val); // AArch64 doesn't force PC alignment, a PC
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// Alignment Fault can be raised instead
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else
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npc(val &~ mask(nextThumb() ? 1 : 2));
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}
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Addr
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instNPC() const
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{
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return npc();
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}
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// Perform an interworking branch.
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void
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instIWNPC(Addr val)
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{
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if (bits(val, 0)) {
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nextThumb(true);
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val = val & ~mask(1);
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} else if (!bits(val, 1)) {
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nextThumb(false);
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} else {
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// This state is UNPREDICTABLE in the ARM architecture
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// The easy thing to do is just mask off the bit and
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// stay in the current mode, so we'll do that.
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val &= ~mask(2);
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}
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npc(val);
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}
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// Perform an interworking branch in ARM mode, a regular branch
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// otherwise.
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void
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instAIWNPC(Addr val)
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{
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if (!thumb())
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instIWNPC(val);
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else
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instNPC(val);
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}
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bool
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equals(const PCStateBase &other) const override
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{
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auto &opc = other.as<PCState>();
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return Base::equals(other) &&
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flags == opc.flags && nextFlags == opc.nextFlags &&
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_itstate == opc._itstate &&
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_nextItstate == opc._nextItstate &&
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_illegalExec == opc._illegalExec &&
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_debugStep == opc._debugStep &&
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_stepped == opc._stepped;
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}
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void
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serialize(CheckpointOut &cp) const override
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{
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Base::serialize(cp);
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SERIALIZE_SCALAR(flags);
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SERIALIZE_SCALAR(_size);
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SERIALIZE_SCALAR(nextFlags);
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SERIALIZE_SCALAR(_itstate);
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SERIALIZE_SCALAR(_nextItstate);
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SERIALIZE_SCALAR(_illegalExec);
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SERIALIZE_SCALAR(_debugStep);
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SERIALIZE_SCALAR(_stepped);
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}
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void
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unserialize(CheckpointIn &cp) override
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{
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Base::unserialize(cp);
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UNSERIALIZE_SCALAR(flags);
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UNSERIALIZE_SCALAR(_size);
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UNSERIALIZE_SCALAR(nextFlags);
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UNSERIALIZE_SCALAR(_itstate);
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UNSERIALIZE_SCALAR(_nextItstate);
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UNSERIALIZE_SCALAR(_illegalExec);
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UNSERIALIZE_SCALAR(_debugStep);
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UNSERIALIZE_SCALAR(_stepped);
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}
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};
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} // namespace ArmISA
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} // namespace gem5
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#endif
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