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gem5/src
Ivana Mitrovic db1c336237 cpu,arch-arm,arch-riscv: adding new instruction types to RISC-V (#589)
This commit adds more detailed instruction types for RISC-V Vector.
Concretely, it substitutes VectorIntegerArith, VectorFloatArith,
VectorIntegerReduce and VectorFloatReduce with more specific types
related to the operation that each instruction (e.g., VectorIntegerAdd
or VectorIntegerMult).

Additionaly, fixes two RISC-V instruction types (VectorXXX) that were
used in ARM SVE, placing the proper SimdXXX ones.

Change-Id: I31774fa6a7cd249abfffec68d11d3d77f08ad70b

CC @adriaarmejach
2024-04-11 10:15:56 -07:00
..
2024-04-10 16:17:57 -04:00