Giacomo Travaglini daa9dcbc0c cpu: O3 switchFreeList checking VecElems instead of FloatRegs ...

Vector elements should be checked instead of floats since those are the
ones mapped to the vector registers.

Change-Id: I36088ab90e63720d846fcf5b43360da105b6c736
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

2019-04-10 08:41:53 +00:00

..

arch

misc: Removed inconsistency in O3* debug msgs

2019-04-03 16:50:22 +00:00

base

dev-arm: Correct cast of template parameter

2019-04-01 15:55:58 +00:00

cpu

cpu: O3 switchFreeList checking VecElems instead of FloatRegs

2019-04-10 08:41:53 +00:00

dev

dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt

2019-04-02 16:20:54 +00:00

doc

docs: Fix power model doxygen

2018-04-20 15:59:35 +00:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

arch, cpu, dev, gpu, mem, sim, python: start using getPort.

2019-03-19 10:22:50 +00:00

kern

kern,sim: implement FUTEX_WAKE_OP

2019-02-08 15:25:30 +00:00

learning_gem5

learning_gem5: Fix vector port panic in SimpleCache

2019-04-08 22:51:38 +00:00

mem

mem: Add a MemBackdoor type to track memory backdoors.

2019-04-06 00:52:15 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

base,python: Fix to allow multiple --debug-ignore values.

2019-03-26 07:25:11 +00:00

sim

arch, cpu, dev, gpu, mem, sim, python: start using getPort.

2019-03-19 10:22:50 +00:00

systemc

systemc: Templatize the gem5/TLM bridge SimObjects.

2019-03-29 22:46:00 +00:00

unittest

python: Replace dict.has_key with 'key in dict'

2019-02-12 17:36:12 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: fix disable_partial logic for fast binary

2019-03-18 22:22:25 +00:00