2194aea053
Fetch in O3CPU mistakes the normal non-branching compressed instructions, and regards it as a branch. This issue interrupts the consecutive instruction stream, thus affecting performance of cpu front-end. This fix sets the compressed for PCState during decoding. Jira Issue: https://gem5.atlassian.net/browse/GEM5-1137 Change-Id: I7607d563bba8a08869e104877fc3c11c94cbe904 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54644 Reviewed-by: Jin Cui <cuijinbird@gmail.com> Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
119 lines
3.6 KiB
C++
119 lines
3.6 KiB
C++
/*
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* Copyright (c) 2012 Google
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* Copyright (c) The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/riscv/decoder.hh"
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#include "arch/riscv/types.hh"
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#include "base/bitfield.hh"
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#include "debug/Decode.hh"
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namespace gem5
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{
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namespace RiscvISA
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{
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void Decoder::reset()
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{
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aligned = true;
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mid = false;
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emi = 0;
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}
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void
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Decoder::moreBytes(const PCStateBase &pc, Addr fetchPC)
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{
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// The MSB of the upper and lower halves of a machine instruction.
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constexpr size_t max_bit = sizeof(machInst) * 8 - 1;
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constexpr size_t mid_bit = sizeof(machInst) * 4 - 1;
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auto inst = letoh(machInst);
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DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst,
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fetchPC);
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bool aligned = pc.instAddr() % sizeof(machInst) == 0;
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if (aligned) {
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emi = inst;
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if (compressed(emi))
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emi = bits(emi, mid_bit, 0);
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outOfBytes = !compressed(emi);
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instDone = true;
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} else {
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if (mid) {
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assert(bits(emi, max_bit, mid_bit + 1) == 0);
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replaceBits(emi, max_bit, mid_bit + 1, inst);
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mid = false;
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outOfBytes = false;
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instDone = true;
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} else {
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emi = bits(inst, max_bit, mid_bit + 1);
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mid = !compressed(emi);
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outOfBytes = true;
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instDone = compressed(emi);
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}
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}
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}
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StaticInstPtr
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Decoder::decode(ExtMachInst mach_inst, Addr addr)
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{
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DPRINTF(Decode, "Decoding instruction 0x%08x at address %#x\n",
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mach_inst, addr);
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StaticInstPtr &si = instMap[mach_inst];
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if (!si)
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si = decodeInst(mach_inst);
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DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
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si->getName(), mach_inst);
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return si;
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}
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StaticInstPtr
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Decoder::decode(PCStateBase &_next_pc)
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{
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if (!instDone)
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return nullptr;
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instDone = false;
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auto &next_pc = _next_pc.as<PCState>();
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if (compressed(emi)) {
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next_pc.npc(next_pc.instAddr() + sizeof(machInst) / 2);
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next_pc.compressed(true);
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} else {
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next_pc.npc(next_pc.instAddr() + sizeof(machInst));
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next_pc.compressed(false);
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}
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return decode(emi, next_pc.instAddr());
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}
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} // namespace RiscvISA
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} // namespace gem5
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