Tiago Mück d8a04f902e mem-cache: add prefetch info to update probe ...

CacheDataUpdateProbeArg has additional info to tell listeners if the
block was prefetched and evicted without being used, as well as which
object prefetched the block.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Change-Id: Id8ac9099ddbce6e94ee775655da23de5df25cf0f
Signed-off-by: Tiago Mück <tiago.muck@arm.com>

2023-11-28 18:30:49 -06:00

..

arch

arch-riscv: Move insts/vector from header to source

2023-10-26 18:04:58 +08:00

base

scons: Explicit the config option HAVE_DEPRECATED_NAMESPACE type bool

2023-10-20 11:41:53 +08:00

cpu

cpu: Branch Predictor Refactoring (#455)

2023-10-26 09:15:11 +01:00

dev

arch-riscv: Add bootloader+kernel workload (#390)

2023-10-18 09:17:12 -07:00

doc

…

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

gpu-compute: Update tokens for flat global/scratch (#408)

2023-10-11 09:00:10 -07:00

kern

misc: Fix buggy special path comparisons

2023-09-05 13:44:10 -07:00

learning_gem5

cpu: Explicitly define cache_line_size -> 64-bit unsigned int (#329)

2023-10-16 07:50:35 -07:00

mem

mem-cache: add prefetch info to update probe

2023-11-28 18:30:49 -06:00

proto

scons: Explicit the config option HAVE_PROTOBUF type boolean

2023-10-20 11:46:02 +08:00

python

arch-riscv: Add bootloader+kernel workload (#390)

2023-10-18 09:17:12 -07:00

sim

sim: Define an InstructionDisassembler SimObject

2023-10-20 09:27:50 +01:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

misc: fix clang13 overloaded-virtual warning (#454)

2023-10-16 07:23:08 -07:00

Doxyfile

misc: Update version info for develop branch

2023-07-10 12:28:44 -07:00

SConscript

python: Add importer to standalone gem5py_m5

2023-09-28 11:22:33 -07:00