Daniel R. Carvalho 2a71435550 mem-cache: Remove extra block init in BaseSetAssoc ...

Removed extra initialization of cache block just after they have been
created and organized the comments.

Change-Id: I75c1beaf0489e3e530fd8cbff2739dc7593e3e6f
Reviewed-on: https://gem5-review.googlesource.com/8661
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

2018-03-01 09:40:06 +00:00

..

arch

sparc: Fix FS Checkpoint loading

2018-02-24 00:28:29 +00:00

base

sim: Make Stats truly non-copy-constructible

2018-02-13 16:47:44 +00:00

cpu

cpu-o3: Don't add non-speculative mem barriers to the IQ twice

2018-02-20 13:30:02 +00:00

dev

sparc: Fix FS Checkpoint loading

2018-02-24 00:28:29 +00:00

doc

sim: Adding support for power models

2016-06-06 17:16:44 +01:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

tarch, mem: Abstract the data stored in the SE page tables.

2018-01-23 20:39:17 +00:00

kern

misc: Updates for gcc7.2 for x86

2017-12-14 00:27:59 +00:00

learning_gem5/part2

learning-gem5: Fix missing misc.hh in hello_object.cc

2017-12-05 21:22:37 +00:00

mem

mem-cache: Remove extra block init in BaseSetAssoc

2018-03-01 09:40:06 +00:00

proto

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

python

arm: DT autogeneration - Device Tree generation methods

2018-01-29 22:21:30 +00:00

sim

sim, power: Temperature used for power calculations

2018-02-28 21:56:08 +00:00

unittest

tests: Turn fbtest into a gtest and move it to src/base.

2017-12-12 19:48:02 +00:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

scons, tests: Fix occasional linking error

2017-12-13 23:57:08 +00:00