073c32be2c
The TARGET_ISA variable would let you select one ISA from a list of possible ISAs. That has now been replaced with USE_ARM_ISA, USE_X86_ISA, etc, variables which are boolean on or off. That will allow any number of ISAs to be enabled or disabled individually. Enabling something other than exactly one of these will probably prevent you from getting a working gem5 binary, but those problems are being addressed in other, parallel change series. I decided to use the USE_ prefix since it was consistent with most other on/off variables we have in gem5. One noteable exception is the BUILD_GPU setting which, you could convincingly argue, is a better prefix than USE_. Another option would be to use CONFIG_, in anticipation of using a kconfig style config mechanism in gem5. It seemed premature to start using a CONFIG_ prefix here, and if we decide to switch to some other prefix like BUILD_, it should be a purposeful choice and not something somebody just starts using. Change-Id: I90fef2835aa4712782e6c1313fbf564d0ed45538 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52491 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Gabe Black <gabe.black@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
107 lines
3.6 KiB
Python
107 lines
3.6 KiB
Python
# Copyright (c) 2012 ARM Limited
|
|
# Copyright (c) 2020 Barkhausen Institut
|
|
# All rights reserved.
|
|
#
|
|
# The license below extends only to copyright in the software and shall
|
|
# not be construed as granting a license to any other intellectual
|
|
# property including but not limited to intellectual property relating
|
|
# to a hardware implementation of the functionality of the software
|
|
# licensed hereunder. You may use the software subject to the license
|
|
# terms below provided that you ensure that this notice is replicated
|
|
# unmodified and in its entirety in all distributions of the software,
|
|
# modified or unmodified, in source code or in binary form.
|
|
#
|
|
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
|
# All rights reserved.
|
|
#
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions are
|
|
# met: redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer;
|
|
# redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
# documentation and/or other materials provided with the distribution;
|
|
# neither the name of the copyright holders nor the names of its
|
|
# contributors may be used to endorse or promote products derived from
|
|
# this software without specific prior written permission.
|
|
#
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
from m5.defines import buildEnv
|
|
from m5.objects import *
|
|
from gem5.isas import ISA
|
|
from gem5.runtime import get_runtime_isa
|
|
|
|
# Base implementations of L1, L2, IO and TLB-walker caches. There are
|
|
# used in the regressions and also as base components in the
|
|
# system-configuration scripts. The values are meant to serve as a
|
|
# starting point, and specific parameters can be overridden in the
|
|
# specific instantiations.
|
|
|
|
|
|
class L1Cache(Cache):
|
|
assoc = 2
|
|
tag_latency = 2
|
|
data_latency = 2
|
|
response_latency = 2
|
|
mshrs = 4
|
|
tgts_per_mshr = 20
|
|
|
|
|
|
class L1_ICache(L1Cache):
|
|
is_read_only = True
|
|
# Writeback clean lines as well
|
|
writeback_clean = True
|
|
|
|
|
|
class L1_DCache(L1Cache):
|
|
pass
|
|
|
|
|
|
class L2Cache(Cache):
|
|
assoc = 8
|
|
tag_latency = 20
|
|
data_latency = 20
|
|
response_latency = 20
|
|
mshrs = 20
|
|
tgts_per_mshr = 12
|
|
write_buffers = 8
|
|
|
|
|
|
class IOCache(Cache):
|
|
assoc = 8
|
|
tag_latency = 50
|
|
data_latency = 50
|
|
response_latency = 50
|
|
mshrs = 20
|
|
size = "1kB"
|
|
tgts_per_mshr = 12
|
|
|
|
|
|
class PageTableWalkerCache(Cache):
|
|
assoc = 2
|
|
tag_latency = 2
|
|
data_latency = 2
|
|
response_latency = 2
|
|
mshrs = 10
|
|
size = "1kB"
|
|
tgts_per_mshr = 12
|
|
|
|
# the x86 table walker actually writes to the table-walker cache
|
|
if get_runtime_isa() in [ISA.X86, ISA.RISCV]:
|
|
is_read_only = False
|
|
else:
|
|
is_read_only = True
|
|
# Writeback clean lines as well
|
|
writeback_clean = True
|