5288dbbf90
- The bytesRead and bytesWritten stat had duplicate names. Updated bytesRead and bytesWritten for dram_interface and nvm_interface Change-Id: I7658e8a0d12ef6b95819bcafa52a85424f01ac76
735 lines
28 KiB
C++
735 lines
28 KiB
C++
/*
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* Copyright (c) 2010-2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2013 Amin Farmahini-Farahani
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mem/nvm_interface.hh"
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#include "base/bitfield.hh"
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#include "base/cprintf.hh"
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#include "base/trace.hh"
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#include "debug/NVM.hh"
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#include "sim/system.hh"
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namespace gem5
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{
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namespace memory
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{
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NVMInterface::NVMInterface(const NVMInterfaceParams &_p)
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: MemInterface(_p),
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maxPendingWrites(_p.max_pending_writes),
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maxPendingReads(_p.max_pending_reads),
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twoCycleRdWr(_p.two_cycle_rdwr),
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tREAD(_p.tREAD), tWRITE(_p.tWRITE), tSEND(_p.tSEND),
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stats(*this),
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writeRespondEvent([this]{ processWriteRespondEvent(); }, name()),
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readReadyEvent([this]{ processReadReadyEvent(); }, name()),
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nextReadAt(0), numPendingReads(0), numReadDataReady(0),
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numReadsToIssue(0)
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{
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DPRINTF(NVM, "Setting up NVM Interface\n");
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fatal_if(!isPowerOf2(burstSize), "NVM burst size %d is not allowed, "
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"must be a power of two\n", burstSize);
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// sanity check the ranks since we rely on bit slicing for the
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// address decoding
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fatal_if(!isPowerOf2(ranksPerChannel), "NVM rank count of %d is "
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"not allowed, must be a power of two\n", ranksPerChannel);
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for (int i =0; i < ranksPerChannel; i++) {
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// Add NVM ranks to the system
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DPRINTF(NVM, "Creating NVM rank %d \n", i);
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Rank* rank = new Rank(_p, i, *this);
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ranks.push_back(rank);
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}
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uint64_t capacity = 1ULL << ceilLog2(AbstractMemory::size());
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DPRINTF(NVM, "NVM capacity %lld (%lld) bytes\n", capacity,
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AbstractMemory::size());
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rowsPerBank = capacity / (rowBufferSize *
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banksPerRank * ranksPerChannel);
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}
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NVMInterface::Rank::Rank(const NVMInterfaceParams &_p,
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int _rank, NVMInterface& _nvm)
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: EventManager(&_nvm), rank(_rank), banks(_p.banks_per_rank)
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{
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for (int b = 0; b < _p.banks_per_rank; b++) {
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banks[b].bank = b;
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// No bank groups; simply assign to bank number
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banks[b].bankgr = b;
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}
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}
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void
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NVMInterface::init()
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{
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AbstractMemory::init();
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}
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void NVMInterface::setupRank(const uint8_t rank, const bool is_read)
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{
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if (is_read) {
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// increment count to trigger read and track number of reads in Q
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numReadsToIssue++;
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} else {
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// increment count to track number of writes in Q
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numWritesQueued++;
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}
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}
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MemPacket*
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NVMInterface::decodePacket(const PacketPtr pkt, Addr pkt_addr,
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unsigned size, bool is_read, uint8_t pseudo_channel)
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{
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// decode the address based on the address mapping scheme, with
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// Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
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// channel, respectively
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uint8_t rank;
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uint8_t bank;
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// use a 64-bit unsigned during the computations as the row is
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// always the top bits, and check before creating the packet
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uint64_t row;
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// Get packed address, starting at 0
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Addr addr = getCtrlAddr(pkt_addr);
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// truncate the address to a memory burst, which makes it unique to
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// a specific buffer, row, bank, rank and channel
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addr = addr / burstSize;
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// we have removed the lowest order address bits that denote the
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// position within the column
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if (addrMapping == enums::RoRaBaChCo || addrMapping == enums::RoRaBaCoCh) {
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// the lowest order bits denote the column to ensure that
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// sequential cache lines occupy the same row
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addr = addr / burstsPerRowBuffer;
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// after the channel bits, get the bank bits to interleave
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// over the banks
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bank = addr % banksPerRank;
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addr = addr / banksPerRank;
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// after the bank, we get the rank bits which thus interleaves
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// over the ranks
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rank = addr % ranksPerChannel;
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addr = addr / ranksPerChannel;
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// lastly, get the row bits, no need to remove them from addr
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row = addr % rowsPerBank;
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} else if (addrMapping == enums::RoCoRaBaCh) {
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// with emerging technologies, could have small page size with
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// interleaving granularity greater than row buffer
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if (burstsPerStripe > burstsPerRowBuffer) {
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// remove column bits which are a subset of burstsPerStripe
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addr = addr / burstsPerRowBuffer;
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} else {
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// remove lower column bits below channel bits
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addr = addr / burstsPerStripe;
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}
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// start with the bank bits, as this provides the maximum
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// opportunity for parallelism between requests
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bank = addr % banksPerRank;
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addr = addr / banksPerRank;
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// next get the rank bits
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rank = addr % ranksPerChannel;
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addr = addr / ranksPerChannel;
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// next, the higher-order column bites
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if (burstsPerStripe < burstsPerRowBuffer) {
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addr = addr / (burstsPerRowBuffer / burstsPerStripe);
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}
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// lastly, get the row bits, no need to remove them from addr
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row = addr % rowsPerBank;
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} else
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panic("Unknown address mapping policy chosen!");
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assert(rank < ranksPerChannel);
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assert(bank < banksPerRank);
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assert(row < rowsPerBank);
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assert(row < Bank::NO_ROW);
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DPRINTF(NVM, "Address: %#x Rank %d Bank %d Row %d\n",
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pkt_addr, rank, bank, row);
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// create the corresponding memory packet with the entry time and
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// ready time set to the current tick, the latter will be updated
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// later
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uint16_t bank_id = banksPerRank * rank + bank;
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return new MemPacket(pkt, is_read, false, pseudo_channel, rank, bank, row,
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bank_id, pkt_addr, size);
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}
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std::pair<MemPacketQueue::iterator, Tick>
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NVMInterface::chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const
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{
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// remember if we found a hit, but one that cannit issue seamlessly
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bool found_prepped_pkt = false;
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auto selected_pkt_it = queue.end();
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Tick selected_col_at = MaxTick;
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for (auto i = queue.begin(); i != queue.end() ; ++i) {
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MemPacket* pkt = *i;
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// select optimal NVM packet in Q
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if (!pkt->isDram()) {
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const Bank& bank = ranks[pkt->rank]->banks[pkt->bank];
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const Tick col_allowed_at = pkt->isRead() ? bank.rdAllowedAt :
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bank.wrAllowedAt;
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// check if rank is not doing a refresh and thus is available,
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// if not, jump to the next packet
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if (burstReady(pkt)) {
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DPRINTF(NVM, "%s bank %d - Rank %d available\n", __func__,
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pkt->bank, pkt->rank);
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// no additional rank-to-rank or media delays
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if (col_allowed_at <= min_col_at) {
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// FCFS within entries that can issue without
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// additional delay, such as same rank accesses
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// or media delay requirements
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selected_pkt_it = i;
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selected_col_at = col_allowed_at;
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// no need to look through the remaining queue entries
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DPRINTF(NVM, "%s Seamless buffer hit\n", __func__);
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break;
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} else if (!found_prepped_pkt) {
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// packet is to prepped region but cannnot issue
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// seamlessly; remember this one and continue
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selected_pkt_it = i;
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selected_col_at = col_allowed_at;
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DPRINTF(NVM, "%s Prepped packet found \n", __func__);
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found_prepped_pkt = true;
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}
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} else {
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DPRINTF(NVM, "%s bank %d - Rank %d not available\n", __func__,
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pkt->bank, pkt->rank);
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}
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}
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}
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if (selected_pkt_it == queue.end()) {
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DPRINTF(NVM, "%s no available NVM ranks found\n", __func__);
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}
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return std::make_pair(selected_pkt_it, selected_col_at);
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}
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void
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NVMInterface::chooseRead(MemPacketQueue& queue)
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{
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Tick cmd_at = std::max(curTick(), nextReadAt);
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// This method does the arbitration between non-deterministic read
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// requests to NVM. The chosen packet is not removed from the queue
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// at this time. Removal from the queue will occur when the data is
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// ready and a separate SEND command is issued to retrieve it via the
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// chooseNext function in the top-level controller.
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assert(!queue.empty());
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assert(numReadsToIssue > 0);
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numReadsToIssue--;
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// For simplicity, issue non-deterministic reads in order (fcfs)
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for (auto i = queue.begin(); i != queue.end() ; ++i) {
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MemPacket* pkt = *i;
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// Find 1st NVM read packet that hasn't issued read command
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if (pkt->readyTime == MaxTick && !pkt->isDram() && pkt->isRead()) {
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// get the bank
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Bank& bank_ref = ranks[pkt->rank]->banks[pkt->bank];
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// issueing a read, inc counter and verify we haven't overrun
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numPendingReads++;
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assert(numPendingReads <= maxPendingReads);
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// increment the bytes accessed and the accesses per row
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bank_ref.bytesAccessed += burstSize;
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// Verify command bandiwth to issue
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// Host can issue read immediately uith buffering closer
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// to the NVM. The actual execution at the NVM may be delayed
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// due to busy resources
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if (twoCycleRdWr) {
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cmd_at = ctrl->verifyMultiCmd(cmd_at,
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maxCommandsPerWindow, tCK);
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} else {
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cmd_at = ctrl->verifySingleCmd(cmd_at,
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maxCommandsPerWindow, false);
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}
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// Update delay to next read
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// Ensures single read command issued per cycle
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nextReadAt = cmd_at + tCK;
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// If accessing a new location in this bank, update timing
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// and stats
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if (bank_ref.openRow != pkt->row) {
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// update the open bank, re-using row field
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bank_ref.openRow = pkt->row;
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// sample the bytes accessed to a buffer in this bank
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// here when we are re-buffering the data
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stats.bytesPerBank.sample(bank_ref.bytesAccessed);
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// start counting anew
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bank_ref.bytesAccessed = 0;
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// holdoff next command to this bank until the read completes
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// and the data has been successfully buffered
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// can pipeline accesses to the same bank, sending them
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// across the interface B2B, but will incur full access
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// delay between data ready responses to different buffers
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// in a bank
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bank_ref.actAllowedAt = std::max(cmd_at,
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bank_ref.actAllowedAt) + tREAD;
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}
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// update per packet readyTime to holdoff burst read operation
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// overloading readyTime, which will be updated again when the
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// burst is issued
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pkt->readyTime = std::max(cmd_at, bank_ref.actAllowedAt);
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DPRINTF(NVM, "Issuing NVM Read to bank %d at tick %d. "
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"Data ready at %d\n",
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bank_ref.bank, cmd_at, pkt->readyTime);
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// Insert into read ready queue. It will be handled after
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// the media delay has been met
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if (readReadyQueue.empty()) {
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assert(!readReadyEvent.scheduled());
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schedule(readReadyEvent, pkt->readyTime);
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} else if (readReadyEvent.when() > pkt->readyTime) {
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// move it sooner in time, to the first read with data
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reschedule(readReadyEvent, pkt->readyTime);
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} else {
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assert(readReadyEvent.scheduled());
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}
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readReadyQueue.push_back(pkt->readyTime);
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// found an NVM read to issue - break out
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break;
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}
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}
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}
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void
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NVMInterface::processReadReadyEvent()
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{
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// signal that there is read data ready to be transmitted
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numReadDataReady++;
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DPRINTF(NVM,
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"processReadReadyEvent(): Data for an NVM read is ready. "
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"numReadDataReady is %d\t numPendingReads is %d\n",
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numReadDataReady, numPendingReads);
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// Find lowest ready time and verify it is equal to curTick
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// also find the next lowest to schedule next event
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// Done with this response, erase entry
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auto ready_it = readReadyQueue.begin();
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Tick next_ready_at = MaxTick;
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for (auto i = readReadyQueue.begin(); i != readReadyQueue.end() ; ++i) {
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if (*ready_it > *i) {
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next_ready_at = *ready_it;
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ready_it = i;
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} else if ((next_ready_at > *i) && (i != ready_it)) {
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next_ready_at = *i;
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}
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}
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// Verify we found the time of this event and remove it
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assert(*ready_it == curTick());
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readReadyQueue.erase(ready_it);
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if (!readReadyQueue.empty()) {
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assert(readReadyQueue.front() >= curTick());
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assert(!readReadyEvent.scheduled());
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schedule(readReadyEvent, next_ready_at);
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}
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// It is possible that a new command kicks things back into
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// action before reaching this point but need to ensure that we
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// continue to process new commands as read data becomes ready
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// This will also trigger a drain if needed
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if (!ctrl->requestEventScheduled()) {
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DPRINTF(NVM, "Restart controller scheduler immediately\n");
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ctrl->restartScheduler(curTick());
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}
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}
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bool
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NVMInterface::burstReady(MemPacket* pkt) const {
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bool read_rdy = pkt->isRead() && (ctrl->inReadBusState(true, this)) &&
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(pkt->readyTime <= curTick()) && (numReadDataReady > 0);
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bool write_rdy = !pkt->isRead() && !ctrl->inReadBusState(true, this) &&
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!writeRespQueueFull();
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return (read_rdy || write_rdy);
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}
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std::pair<Tick, Tick>
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NVMInterface::doBurstAccess(MemPacket* pkt, Tick next_burst_at,
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const std::vector<MemPacketQueue>& queue)
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{
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DPRINTF(NVM, "NVM Timing access to addr %#x, rank/bank/row %d %d %d\n",
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pkt->addr, pkt->rank, pkt->bank, pkt->row);
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// get the bank
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Bank& bank_ref = ranks[pkt->rank]->banks[pkt->bank];
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// respect any constraints on the command
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const Tick bst_allowed_at = pkt->isRead() ?
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bank_ref.rdAllowedAt : bank_ref.wrAllowedAt;
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// we need to wait until the bus is available before we can issue
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// the command; need minimum of tBURST between commands
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Tick cmd_at = std::max(bst_allowed_at, curTick());
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// we need to wait until the bus is available before we can issue
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// the command; need minimum of tBURST between commands
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cmd_at = std::max(cmd_at, next_burst_at);
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// Verify there is command bandwidth to issue
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// Read burst (send command) is a simple data access and only requires
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// one command cycle
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// Write command may require multiple cycles to enable larger address space
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if (pkt->isRead() || !twoCycleRdWr) {
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cmd_at = ctrl->verifySingleCmd(cmd_at, maxCommandsPerWindow, false);
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} else {
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cmd_at = ctrl->verifyMultiCmd(cmd_at, maxCommandsPerWindow, tCK);
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}
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// update the packet ready time to reflect when data will be transferred
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// Use the same bus delays defined for NVM
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pkt->readyTime = cmd_at + tSEND + tBURST;
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Tick dly_to_rd_cmd;
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Tick dly_to_wr_cmd;
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for (auto n : ranks) {
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for (int i = 0; i < banksPerRank; i++) {
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// base delay is a function of tBURST and bus turnaround
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dly_to_rd_cmd = pkt->isRead() ? tBURST : writeToReadDelay();
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dly_to_wr_cmd = pkt->isRead() ? readToWriteDelay() : tBURST;
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if (pkt->rank != n->rank) {
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// adjust timing for different ranks
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// Need to account for rank-to-rank switching with tCS
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dly_to_wr_cmd = rankToRankDelay();
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dly_to_rd_cmd = rankToRankDelay();
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}
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n->banks[i].rdAllowedAt = std::max(cmd_at + dly_to_rd_cmd,
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n->banks[i].rdAllowedAt);
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n->banks[i].wrAllowedAt = std::max(cmd_at + dly_to_wr_cmd,
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n->banks[i].wrAllowedAt);
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}
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}
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DPRINTF(NVM, "NVM Access to %#x, ready at %lld.\n",
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pkt->addr, pkt->readyTime);
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if (pkt->isRead()) {
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// completed the read, decrement counters
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assert(numPendingReads != 0);
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assert(numReadDataReady != 0);
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numPendingReads--;
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numReadDataReady--;
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} else {
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// Adjust number of NVM writes in Q
|
|
assert(numWritesQueued > 0);
|
|
numWritesQueued--;
|
|
|
|
// increment the bytes accessed and the accesses per row
|
|
// only increment for writes as the reads are handled when
|
|
// the non-deterministic read is issued, before the data transfer
|
|
bank_ref.bytesAccessed += burstSize;
|
|
|
|
// Commands will be issued serially when accessing the same bank
|
|
// Commands can issue in parallel to different banks
|
|
if ((bank_ref.bank == pkt->bank) &&
|
|
(bank_ref.openRow != pkt->row)) {
|
|
// update the open buffer, re-using row field
|
|
bank_ref.openRow = pkt->row;
|
|
|
|
// sample the bytes accessed to a buffer in this bank
|
|
// here when we are re-buffering the data
|
|
stats.bytesPerBank.sample(bank_ref.bytesAccessed);
|
|
// start counting anew
|
|
bank_ref.bytesAccessed = 0;
|
|
}
|
|
|
|
// Determine when write will actually complete, assuming it is
|
|
// scheduled to push to NVM immediately
|
|
// update actAllowedAt to serialize next command completion that
|
|
// accesses this bank; must wait until this write completes
|
|
// Data accesses to the same buffer in this bank
|
|
// can issue immediately after actAllowedAt expires, without
|
|
// waiting additional delay of tWRITE. Can revisit this
|
|
// assumption/simplification in the future.
|
|
bank_ref.actAllowedAt = std::max(pkt->readyTime,
|
|
bank_ref.actAllowedAt) + tWRITE;
|
|
|
|
// Need to track number of outstanding writes to
|
|
// ensure 'buffer' on media controller does not overflow
|
|
assert(!writeRespQueueFull());
|
|
|
|
// Insert into write done queue. It will be handled after
|
|
// the media delay has been met
|
|
if (writeRespQueueEmpty()) {
|
|
assert(!writeRespondEvent.scheduled());
|
|
schedule(writeRespondEvent, bank_ref.actAllowedAt);
|
|
} else {
|
|
assert(writeRespondEvent.scheduled());
|
|
}
|
|
writeRespQueue.push_back(bank_ref.actAllowedAt);
|
|
writeRespQueue.sort();
|
|
if (writeRespondEvent.when() > bank_ref.actAllowedAt) {
|
|
DPRINTF(NVM, "Rescheduled respond event from %lld to %11d\n",
|
|
writeRespondEvent.when(), bank_ref.actAllowedAt);
|
|
DPRINTF(NVM, "Front of response queue is %11d\n",
|
|
writeRespQueue.front());
|
|
reschedule(writeRespondEvent, bank_ref.actAllowedAt);
|
|
}
|
|
|
|
}
|
|
|
|
// Update the stats
|
|
if (pkt->isRead()) {
|
|
stats.readBursts++;
|
|
stats.nvmBytesRead += burstSize;
|
|
stats.perBankRdBursts[pkt->bankId]++;
|
|
stats.pendingReads.sample(numPendingReads);
|
|
|
|
// Update latency stats
|
|
stats.totMemAccLat += pkt->readyTime - pkt->entryTime;
|
|
stats.totBusLat += tBURST;
|
|
stats.totQLat += cmd_at - pkt->entryTime;
|
|
} else {
|
|
stats.writeBursts++;
|
|
stats.nvmBytesWritten += burstSize;
|
|
stats.perBankWrBursts[pkt->bankId]++;
|
|
}
|
|
|
|
return std::make_pair(cmd_at, cmd_at + tBURST);
|
|
}
|
|
|
|
void
|
|
NVMInterface::processWriteRespondEvent()
|
|
{
|
|
DPRINTF(NVM,
|
|
"processWriteRespondEvent(): A NVM write reached its readyTime. "
|
|
"%d remaining pending NVM writes\n", writeRespQueue.size());
|
|
|
|
// Update stat to track histogram of pending writes
|
|
stats.pendingWrites.sample(writeRespQueue.size());
|
|
|
|
// Done with this response, pop entry
|
|
writeRespQueue.pop_front();
|
|
|
|
if (!writeRespQueue.empty()) {
|
|
assert(writeRespQueue.front() >= curTick());
|
|
assert(!writeRespondEvent.scheduled());
|
|
schedule(writeRespondEvent, writeRespQueue.front());
|
|
}
|
|
|
|
// It is possible that a new command kicks things back into
|
|
// action before reaching this point but need to ensure that we
|
|
// continue to process new commands as writes complete at the media and
|
|
// credits become available. This will also trigger a drain if needed
|
|
if (!ctrl->requestEventScheduled()) {
|
|
DPRINTF(NVM, "Restart controller scheduler immediately\n");
|
|
ctrl->restartScheduler(curTick());
|
|
}
|
|
}
|
|
|
|
void
|
|
NVMInterface::addRankToRankDelay(Tick cmd_at)
|
|
{
|
|
// update timing for NVM ranks due to bursts issued
|
|
// to ranks for other media interfaces
|
|
for (auto n : ranks) {
|
|
for (int i = 0; i < banksPerRank; i++) {
|
|
// different rank by default
|
|
// Need to only account for rank-to-rank switching
|
|
n->banks[i].rdAllowedAt = std::max(cmd_at + rankToRankDelay(),
|
|
n->banks[i].rdAllowedAt);
|
|
n->banks[i].wrAllowedAt = std::max(cmd_at + rankToRankDelay(),
|
|
n->banks[i].wrAllowedAt);
|
|
}
|
|
}
|
|
}
|
|
|
|
bool
|
|
NVMInterface::isBusy(bool read_queue_empty, bool all_writes_nvm)
|
|
{
|
|
DPRINTF(NVM,"isBusy: numReadDataReady = %d\n", numReadDataReady);
|
|
// Determine NVM is busy and cannot issue a burst
|
|
// A read burst cannot issue when data is not ready from the NVM
|
|
// Also check that we have reads queued to ensure we can change
|
|
// bus direction to service potential write commands.
|
|
// A write cannot issue once we've reached MAX pending writes
|
|
// Only assert busy for the write case when there are also
|
|
// no reads in Q and the write queue only contains NVM commands
|
|
// This allows the bus state to switch and service reads
|
|
return (ctrl->inReadBusState(true, this) ?
|
|
(numReadDataReady == 0) && !read_queue_empty :
|
|
writeRespQueueFull() && read_queue_empty &&
|
|
all_writes_nvm);
|
|
}
|
|
|
|
NVMInterface::NVMStats::NVMStats(NVMInterface &_nvm)
|
|
: statistics::Group(&_nvm),
|
|
nvm(_nvm),
|
|
|
|
ADD_STAT(readBursts, statistics::units::Count::get(),
|
|
"Number of NVM read bursts"),
|
|
ADD_STAT(writeBursts, statistics::units::Count::get(),
|
|
"Number of NVM write bursts"),
|
|
|
|
ADD_STAT(perBankRdBursts, statistics::units::Count::get(),
|
|
"Per bank write bursts"),
|
|
ADD_STAT(perBankWrBursts, statistics::units::Count::get(),
|
|
"Per bank write bursts"),
|
|
|
|
ADD_STAT(totQLat, statistics::units::Tick::get(),
|
|
"Total ticks spent queuing"),
|
|
ADD_STAT(totBusLat, statistics::units::Tick::get(),
|
|
"Total ticks spent in databus transfers"),
|
|
ADD_STAT(totMemAccLat, statistics::units::Tick::get(),
|
|
"Total ticks spent from burst creation until serviced "
|
|
"by the NVM"),
|
|
ADD_STAT(avgQLat, statistics::units::Rate<
|
|
statistics::units::Tick, statistics::units::Count>::get(),
|
|
"Average queueing delay per NVM burst"),
|
|
ADD_STAT(avgBusLat, statistics::units::Rate<
|
|
statistics::units::Tick, statistics::units::Count>::get(),
|
|
"Average bus latency per NVM burst"),
|
|
ADD_STAT(avgMemAccLat, statistics::units::Rate<
|
|
statistics::units::Tick, statistics::units::Count>::get(),
|
|
"Average memory access latency per NVM burst"),
|
|
|
|
ADD_STAT(nvmBytesRead, statistics::units::Byte::get(),
|
|
"Total bytes read"),
|
|
ADD_STAT(nvmBytesWritten, statistics::units::Byte::get(),
|
|
"Total bytes written"),
|
|
|
|
ADD_STAT(avgRdBW, statistics::units::Rate<
|
|
statistics::units::Byte, statistics::units::Second>::get(),
|
|
"Average DRAM read bandwidth in MiBytes/s"),
|
|
ADD_STAT(avgWrBW, statistics::units::Rate<
|
|
statistics::units::Byte, statistics::units::Second>::get(),
|
|
"Average DRAM write bandwidth in MiBytes/s"),
|
|
ADD_STAT(peakBW, statistics::units::Rate<
|
|
statistics::units::Byte, statistics::units::Second>::get(),
|
|
"Theoretical peak bandwidth in MiByte/s"),
|
|
ADD_STAT(busUtil, statistics::units::Ratio::get(),
|
|
"NVM Data bus utilization in percentage"),
|
|
ADD_STAT(busUtilRead, statistics::units::Ratio::get(),
|
|
"NVM Data bus read utilization in percentage"),
|
|
ADD_STAT(busUtilWrite, statistics::units::Ratio::get(),
|
|
"NVM Data bus write utilization in percentage"),
|
|
|
|
ADD_STAT(pendingReads, statistics::units::Count::get(),
|
|
"Reads issued to NVM for which data has not been transferred"),
|
|
ADD_STAT(pendingWrites, statistics::units::Count::get(),
|
|
"Number of outstanding writes to NVM"),
|
|
ADD_STAT(bytesPerBank, statistics::units::Byte::get(),
|
|
"Bytes read within a bank before loading new bank")
|
|
|
|
{
|
|
}
|
|
|
|
void
|
|
NVMInterface::NVMStats::regStats()
|
|
{
|
|
using namespace statistics;
|
|
|
|
perBankRdBursts.init(nvm.ranksPerChannel == 0 ? 1 :
|
|
nvm.banksPerRank * nvm.ranksPerChannel);
|
|
|
|
perBankWrBursts.init(nvm.ranksPerChannel == 0 ? 1 :
|
|
nvm.banksPerRank * nvm.ranksPerChannel);
|
|
|
|
avgQLat.precision(2);
|
|
avgBusLat.precision(2);
|
|
avgMemAccLat.precision(2);
|
|
|
|
avgRdBW.precision(2);
|
|
avgWrBW.precision(2);
|
|
peakBW.precision(2);
|
|
|
|
busUtil.precision(2);
|
|
busUtilRead.precision(2);
|
|
busUtilWrite.precision(2);
|
|
|
|
pendingReads
|
|
.init(nvm.maxPendingReads)
|
|
.flags(nozero);
|
|
|
|
pendingWrites
|
|
.init(nvm.maxPendingWrites)
|
|
.flags(nozero);
|
|
|
|
bytesPerBank
|
|
.init(nvm.rowBufferSize)
|
|
.flags(nozero);
|
|
|
|
avgQLat = totQLat / readBursts;
|
|
avgBusLat = totBusLat / readBursts;
|
|
avgMemAccLat = totMemAccLat / readBursts;
|
|
|
|
avgRdBW = (nvmBytesRead / 1000000) / simSeconds;
|
|
avgWrBW = (nvmBytesWritten / 1000000) / simSeconds;
|
|
peakBW = (sim_clock::Frequency / nvm.tBURST) *
|
|
nvm.burstSize / 1000000;
|
|
|
|
busUtil = (avgRdBW + avgWrBW) / peakBW * 100;
|
|
busUtilRead = avgRdBW / peakBW * 100;
|
|
busUtilWrite = avgWrBW / peakBW * 100;
|
|
}
|
|
|
|
} // namespace memory
|
|
} // namespace gem5
|