Mitch Hayenga ccf4f6c3d7 arm: Change TLB Software Caching ...

In ARM, certain variables are only updated when a necessary change is
detected.  Having 2 SMT threads share a TLB resulted in these not being
updated as required.  This patch adds a thread context identifer to
assist in the invalidation of these variables.

2015-09-30 11:14:19 -05:00

..

freebsd

arch: fix build under MacOSX

2015-06-07 14:02:40 -05:00

insts

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

isa

isa,cpu: Add support for FS SMT Interrupts

2015-09-30 11:14:19 -05:00

kvm

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

linux

cpu: Move invldPid constant from Request to BaseCPU

2015-08-21 07:03:14 -04:00

ArmInterrupts.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

ArmISA.py

arm: Add a model of an ARM PMUv3

2014-10-16 05:49:39 -04:00

ArmNativeTrace.py

cpu: Put all CPU instruction tracers in a single file

2015-01-25 07:22:17 -05:00

ArmPMU.py

arm: Add helper methods to setup architected PMU events

2014-10-16 05:49:42 -04:00

ArmSystem.py

arm: Get rid of pointless have_generic_timer param

2015-05-23 13:46:54 +01:00

ArmTLB.py

arm: Share a port for the two table walker objects

2015-03-02 04:00:42 -05:00

ccregs.hh

arm: use condition code registers for ARM ISA

2014-04-29 16:05:02 -05:00

decoder.cc

arm: Raise an alignment fault if a PC has illegal alignment

2014-12-23 09:31:17 -05:00

decoder.hh

arm: Clean up and document decoder API

2014-12-23 09:31:17 -05:00

faults.cc

isa,cpu: Add support for FS SMT Interrupts

2015-09-30 11:14:19 -05:00

faults.hh

arm: Fixes based on UBSan and static analysis

2014-11-14 03:53:51 -05:00

interrupts.cc

arm: Add support for ARMv8 (AArch64 & AArch32)

2014-01-24 15:29:34 -06:00

interrupts.hh

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

intregs.hh

arm: ISA X31 destination register fix

2014-09-03 07:42:43 -04:00

isa_device.cc

arm: Add support for filtering in the PMU

2014-12-23 09:31:17 -05:00

isa_device.hh

arm: Add support for filtering in the PMU

2014-12-23 09:31:17 -05:00

isa_traits.hh

arch: Cleanup unused ISA traits constants

2014-09-03 07:42:21 -04:00

isa.cc

isa,cpu: Add support for FS SMT Interrupts

2015-09-30 11:14:19 -05:00

isa.hh

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

kernel_stats.hh

Make commenting on close namespace brackets consistent.

2011-01-03 14:35:43 -08:00

locked_mem.hh

cpu,isa,mem: Add per-thread wakeup logic

2015-09-30 11:14:19 -05:00

microcode_rom.hh

arm: include missing file for arm

2009-04-21 15:40:26 -07:00

miscregs.cc

arm: implement the CONTEXTIDR_EL2 system reg.

2015-05-26 03:21:45 -04:00

miscregs.hh

arm: implement the CONTEXTIDR_EL2 system reg.

2015-05-26 03:21:45 -04:00

mmapped_ipr.hh

arch: Add support for m5ops using mmapped IPRs

2013-09-30 12:20:43 +02:00

nativetrace.cc

arm: use condition code registers for ARM ISA

2014-04-29 16:05:02 -05:00

nativetrace.hh

ARM: Add vfpv3 support to native trace.

2011-05-04 20:38:26 -05:00

pagetable.hh

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

pmu.cc

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

pmu.hh

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

process.cc

arch, base, dev, kern, sym: FreeBSD support

2015-04-29 22:35:23 -05:00

process.hh

arm: Fixes based on UBSan and static analysis

2014-11-14 03:53:51 -05:00

pseudo_inst.hh

kvm, x86: Adding support for SE mode execution

2014-11-23 18:01:08 -08:00

registers.hh

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

remote_gdb.cc

arm: Correctly access the stack pointer in GDB

2015-03-02 04:00:27 -05:00

remote_gdb.hh

misc: Appease gcc 5.1 without moving GDB_REG_BYTES

2015-04-24 03:30:08 -04:00

SConscript

arch, base, dev, kern, sym: FreeBSD support

2015-04-29 22:35:23 -05:00

SConsopts

arm: add ARM support to M5

2009-04-05 18:53:15 -07:00

stacktrace.cc

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

stacktrace.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

stage2_lookup.cc

arch: Pass faults by const reference where possible

2014-09-19 10:35:18 -04:00

stage2_lookup.hh

sim: Move the BaseTLB to src/arch/generic/

2015-02-11 10:23:27 -05:00

stage2_mmu.cc

sim: Decouple draining from the SimObject hierarchy

2015-07-07 09:51:05 +01:00

stage2_mmu.hh

sim: Decouple draining from the SimObject hierarchy

2015-07-07 09:51:05 +01:00

system.cc

arm: Get rid of pointless have_generic_timer param

2015-05-23 13:46:54 +01:00

system.hh

arm: Get rid of pointless have_generic_timer param

2015-05-23 13:46:54 +01:00

table_walker.cc

sim: Refactor and simplify the drain API

2015-07-07 09:51:05 +01:00

table_walker.hh

sim: Refactor and simplify the drain API

2015-07-07 09:51:05 +01:00

tlb.cc

arm: Change TLB Software Caching

2015-09-30 11:14:19 -05:00

tlb.hh

arm: Change TLB Software Caching

2015-09-30 11:14:19 -05:00

types.hh

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

utility.cc

arm: SMT MPIDR Setting

2015-09-30 11:14:19 -05:00

utility.hh

arm: Make address translation faster with better caching

2015-05-26 03:21:42 -04:00

vtophys.cc

arm: Fix broken page table permissions checks in remote GDB

2015-03-02 04:00:27 -05:00

vtophys.hh

gcc: Clean-up of non-C++0x compliant code, first steps

2012-03-19 06:36:09 -04:00