Gabe Black e01ead41c2 scons,arch: Remove simple scalar compatibility. ...

This was primarily in Alpha where disassmbly output could be compatible
(default off, probably not usd in a long time), and floating point
could be compatible (default on). A small bit had crept into x86 from
long ago which is also removed.

Change-Id: Ibb68b63787f370259bd1613b393e0b057c007704
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25012
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-02-13 19:59:41 +00:00

..

alpha

scons,arch: Remove simple scalar compatibility.

2020-02-13 19:59:41 +00:00

arm

arm: "Correct" the spelling of flavor.

2020-02-13 19:39:40 +00:00

generic

arch: Get rid of the generic mmapped IPR mechanism.

2020-02-11 11:58:06 +00:00

hsail

arch-hsail: changed gen.py shebang from python(3) to python2.7

2019-03-11 22:13:24 +00:00

mips

arch: Get rid of the generic mmapped IPR mechanism.

2020-02-11 11:58:06 +00:00

null

arch,sim: Merge initCPU into the ISA System classes.

2020-02-01 12:31:56 +00:00

power

arch: Get rid of the generic mmapped IPR mechanism.

2020-02-11 11:58:06 +00:00

riscv

arch: Get rid of the generic mmapped IPR mechanism.

2020-02-11 11:58:06 +00:00

sparc

arch: Get rid of the generic mmapped IPR mechanism.

2020-02-11 11:58:06 +00:00

x86

scons,arch: Remove simple scalar compatibility.

2020-02-13 19:59:41 +00:00

isa_parser.py

arch: Add include guards to auto-gen. decode header

2019-05-30 15:56:17 +00:00

micro_asm_test.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

micro_asm.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

SConscript

arch: Remove the "interrupts.hh" switching header file.

2019-10-19 01:46:00 +00:00