64171d4d14
This can be used for DPRINTFs related to those registers using DPRINTFV. Change-Id: I0fccb12b70fdb74e01022fe0d3d9c2f92425a5bf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49696 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
86 lines
3.3 KiB
C++
86 lines
3.3 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/power/isa.hh"
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#include "arch/power/regs/float.hh"
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#include "arch/power/regs/int.hh"
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#include "arch/power/regs/misc.hh"
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#include "cpu/thread_context.hh"
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#include "debug/FloatRegs.hh"
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#include "debug/IntRegs.hh"
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#include "debug/MiscRegs.hh"
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#include "params/PowerISA.hh"
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namespace gem5
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{
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namespace PowerISA
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{
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ISA::ISA(const Params &p) : BaseISA(p)
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{
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_regClasses.emplace_back(NumIntRegs, debug::IntRegs, NumIntRegs - 1);
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_regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
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_regClasses.emplace_back(1, debug::IntRegs);
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_regClasses.emplace_back(2, debug::IntRegs);
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_regClasses.emplace_back(1, debug::IntRegs);
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_regClasses.emplace_back(0, debug::IntRegs);
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_regClasses.emplace_back(NUM_MISCREGS, debug::MiscRegs);
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clear();
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}
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void
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ISA::copyRegsFrom(ThreadContext *src)
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{
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// First loop through the integer registers.
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for (int i = 0; i < NumIntRegs; ++i)
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tc->setIntReg(i, src->readIntReg(i));
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// Then loop through the floating point registers.
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for (int i = 0; i < NumFloatRegs; ++i)
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tc->setFloatReg(i, src->readFloatReg(i));
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//TODO Copy misc. registers
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// Lastly copy PC/NPC
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tc->pcState(src->pcState());
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}
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} // namespace PowerISA
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} // namespace gem5
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