4c42811ff3
This change moves some stats that are used in SLICC to a
separate Stats::Group.
In order to use stats in SLICC, new functions are added in
CacheMemory:
- profileDemandHit()
- profileDemandMiss()
The functions increase the corresponding stat by 1.
Change-Id: I52b6fefdf6579a49f626f2fca400641f90800017
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37815
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
1182 lines
39 KiB
Plaintext
1182 lines
39 KiB
Plaintext
/*
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* Copyright (c) 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2013 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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machine(MachineType:L0Cache, "MESI Directory L0 Cache")
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: Sequencer * sequencer;
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CacheMemory * Icache;
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CacheMemory * Dcache;
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Cycles request_latency := 2;
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Cycles response_latency := 2;
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bool send_evictions;
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RubyPrefetcher * prefetcher;
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bool enable_prefetch := "False";
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// From this node's L0 cache to the network
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MessageBuffer * bufferToL1, network="To";
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// To this node's L0 cache FROM the network
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MessageBuffer * bufferFromL1, network="From";
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// Message queue between this controller and the processor
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MessageBuffer * mandatoryQueue;
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// Request Buffer for prefetches
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MessageBuffer * prefetchQueue;
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{
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// STATES
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state_declaration(State, desc="Cache states", default="L0Cache_State_I") {
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// Base states
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// The cache entry has not been allocated.
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I, AccessPermission:Invalid, desc="Invalid";
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// The cache entry is in shared mode. The processor can read this entry
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// but it cannot write to it.
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S, AccessPermission:Read_Only, desc="Shared";
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// The cache entry is in exclusive mode. The processor can read this
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// entry. It can write to this entry without informing the directory.
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// On writing, the entry moves to M state.
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E, AccessPermission:Read_Only, desc="Exclusive";
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// The processor has read and write permissions on this entry.
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M, AccessPermission:Read_Write, desc="Modified";
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// Transient States
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// The cache controller has requested an instruction. It will be stored
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// in the shared state so that the processor can read it.
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Inst_IS, AccessPermission:Busy, desc="Issued GETS, have not seen response yet";
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// The cache controller has requested that this entry be fetched in
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// shared state so that the processor can read it.
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IS, AccessPermission:Busy, desc="Issued GETS, have not seen response yet";
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// The cache controller has requested that this entry be fetched in
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// modify state so that the processor can read/write it.
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IM, AccessPermission:Busy, desc="Issued GETX, have not seen response yet";
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// The cache controller had read permission over the entry. But now the
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// processor needs to write to it. So, the controller has requested for
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// write permission.
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SM, AccessPermission:Read_Only, desc="Issued GETX, have not seen response yet";
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// Transient states in which block is being prefetched
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PF_Inst_IS, AccessPermission:Busy, desc="Issued GETS, have not seen response yet";
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PF_IS, AccessPermission:Busy, desc="Issued GETS, have not seen response yet";
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PF_IE, AccessPermission:Busy, desc="Issued GETX, have not seen response yet";
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}
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// EVENTS
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enumeration(Event, desc="Cache events") {
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// Events from core
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Load, desc="Load request from the home processor";
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Ifetch, desc="I-fetch request from the home processor";
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Store, desc="Store request from the home processor";
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// invalidations from L1 (due to self or other core)
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InvOwn, desc="Invalidate request from L1 (own)";
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InvElse, desc="Invalidate request from L1 (else)";
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// internal generated request
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L0_Replacement, desc="L0 Replacement", format="!r";
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// requests forwarded from other processors
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Fwd_GETX, desc="GETX from other processor";
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Fwd_GETS, desc="GETS from other processor";
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Fwd_GET_INSTR, desc="GET_INSTR from other processor";
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// data arrives from L1 cache
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Data, desc="Data for processor";
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Data_Exclusive, desc="Data for processor";
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Data_Stale, desc="Data for processor, but not for storage";
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Ack, desc="Ack for processor";
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WB_Ack, desc="Ack for replacement";
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Failed_SC, desc="Store conditional request that will fail";
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// Prefetch events (generated by prefetcher)
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PF_L0_Replacement, desc="L0 Replacement caused by pretcher", format="!pr";
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PF_Load, desc="Load request from prefetcher";
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PF_Ifetch, desc="Instruction fetch request from prefetcher";
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PF_Store, desc="Exclusive load request from prefetcher";
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PF_Bad_Addr, desc="Throw away prefetch request due to bad address generation";
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}
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// TYPES
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// CacheEntry
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structure(Entry, desc="...", interface="AbstractCacheEntry" ) {
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State CacheState, desc="cache state";
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DataBlock DataBlk, desc="data for the block";
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bool Dirty, default="false", desc="data is dirty";
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bool isPrefetched, default="false", desc="Set if this block was prefetched";
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}
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// TBE fields
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structure(TBE, desc="...") {
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Addr addr, desc="Physical address for this TBE";
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="Buffer for the data block";
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bool Dirty, default="false", desc="data is dirty";
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int pendingAcks, default="0", desc="number of pending acks";
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}
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structure(TBETable, external="yes") {
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TBE lookup(Addr);
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void allocate(Addr);
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void deallocate(Addr);
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bool isPresent(Addr);
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TBE getNullEntry();
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}
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TBETable TBEs, template="<L0Cache_TBE>", constructor="m_number_of_TBEs";
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Tick clockEdge();
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Cycles ticksToCycles(Tick t);
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void set_cache_entry(AbstractCacheEntry a);
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void unset_cache_entry();
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void set_tbe(TBE a);
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void unset_tbe();
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void wakeUpBuffers(Addr a);
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void wakeUpAllBuffers(Addr a);
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void profileMsgDelay(int virtualNetworkType, Cycles c);
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MachineID mapAddressToMachine(Addr addr, MachineType mtype);
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// inclusive cache returns L0 entries only
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Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
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Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
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if(is_valid(Dcache_entry)) {
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return Dcache_entry;
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}
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Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]);
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return Icache_entry;
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}
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Entry getDCacheEntry(Addr addr), return_by_pointer="yes" {
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Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
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return Dcache_entry;
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}
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Entry getICacheEntry(Addr addr), return_by_pointer="yes" {
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Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]);
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return Icache_entry;
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}
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State getState(TBE tbe, Entry cache_entry, Addr addr) {
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assert((Dcache.isTagPresent(addr) && Icache.isTagPresent(addr)) == false);
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if(is_valid(tbe)) {
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return tbe.TBEState;
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} else if (is_valid(cache_entry)) {
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return cache_entry.CacheState;
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}
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return State:I;
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}
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void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
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assert((Dcache.isTagPresent(addr) && Icache.isTagPresent(addr)) == false);
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// MUST CHANGE
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if(is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (is_valid(cache_entry)) {
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cache_entry.CacheState := state;
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}
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}
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AccessPermission getAccessPermission(Addr addr) {
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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DPRINTF(RubySlicc, "%s\n", L0Cache_State_to_permission(tbe.TBEState));
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return L0Cache_State_to_permission(tbe.TBEState);
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}
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Entry cache_entry := getCacheEntry(addr);
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if(is_valid(cache_entry)) {
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DPRINTF(RubySlicc, "%s\n", L0Cache_State_to_permission(cache_entry.CacheState));
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return L0Cache_State_to_permission(cache_entry.CacheState);
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}
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DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
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return AccessPermission:NotPresent;
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}
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void functionalRead(Addr addr, Packet *pkt) {
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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testAndRead(addr, tbe.DataBlk, pkt);
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} else {
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testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
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}
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}
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int functionalWrite(Addr addr, Packet *pkt) {
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int num_functional_writes := 0;
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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num_functional_writes := num_functional_writes +
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testAndWrite(addr, tbe.DataBlk, pkt);
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return num_functional_writes;
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}
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num_functional_writes := num_functional_writes +
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testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
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return num_functional_writes;
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}
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void setAccessPermission(Entry cache_entry, Addr addr, State state) {
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if (is_valid(cache_entry)) {
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cache_entry.changePermission(L0Cache_State_to_permission(state));
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}
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}
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Event mandatory_request_type_to_event(RubyRequestType type) {
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if (type == RubyRequestType:LD) {
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return Event:Load;
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} else if (type == RubyRequestType:IFETCH) {
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return Event:Ifetch;
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} else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)
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|| (type == RubyRequestType:Store_Conditional)) {
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return Event:Store;
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} else {
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error("Invalid RubyRequestType");
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}
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}
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Event prefetch_request_type_to_event(RubyRequestType type) {
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if (type == RubyRequestType:LD) {
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return Event:PF_Load;
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} else if (type == RubyRequestType:IFETCH) {
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return Event:PF_Ifetch;
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} else if (type == RubyRequestType:ST) {
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return Event:PF_Store;
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} else {
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error("Invalid RubyRequestType");
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}
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}
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int getPendingAcks(TBE tbe) {
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return tbe.pendingAcks;
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}
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out_port(requestNetwork_out, CoherenceMsg, bufferToL1);
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out_port(optionalQueue_out, RubyRequest, prefetchQueue);
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void enqueuePrefetch(Addr address, RubyRequestType type) {
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enqueue(optionalQueue_out, RubyRequest, 1) {
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out_msg.LineAddress := address;
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out_msg.Type := type;
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out_msg.Prefetch := PrefetchBit:Yes;
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out_msg.AccessMode := RubyAccessMode:Supervisor;
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}
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}
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// Prefetch queue between the controller and the prefetcher
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// As per Spracklen et al. (HPCA 2005), the prefetch queue should be
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// implemented as a LIFO structure. The structure would allow for fast
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// searches of all entries in the queue, not just the head msg. All
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// msgs in the structure can be invalidated if a demand miss matches.
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in_port(optionalQueue_in, RubyRequest, prefetchQueue, desc="...", rank = 2) {
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if (optionalQueue_in.isReady(clockEdge())) {
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peek(optionalQueue_in, RubyRequest) {
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// first check for valid address
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MachineID mid := mapAddressToMachine(in_msg.LineAddress, MachineType:Directory);
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NodeID nid := machineIDToNodeID(mid);
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int nidint := IDToInt(nid);
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int numDirs := machineCount(MachineType:Directory);
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if (nidint >= numDirs) {
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Entry cache_entry := static_cast(Entry, "pointer", Dcache.getNullEntry());
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TBE tbe := TBEs.getNullEntry();
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trigger(Event:PF_Bad_Addr, in_msg.LineAddress, cache_entry, tbe);
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} else if (in_msg.Type == RubyRequestType:IFETCH) {
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// Instruction Prefetch
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Entry icache_entry := getICacheEntry(in_msg.LineAddress);
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if (is_valid(icache_entry)) {
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// The block to be prefetched is already present in the
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// cache. This request will be made benign and cause the
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// prefetch queue to be popped.
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trigger(prefetch_request_type_to_event(in_msg.Type),
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in_msg.LineAddress,
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icache_entry, TBEs[in_msg.LineAddress]);
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}
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// Check to see if it is in the L0-D
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Entry cache_entry := getDCacheEntry(in_msg.LineAddress);
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if (is_valid(cache_entry)) {
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// The block is in the wrong L0 cache. We should drop
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// this request.
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trigger(prefetch_request_type_to_event(in_msg.Type),
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in_msg.LineAddress,
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cache_entry, TBEs[in_msg.LineAddress]);
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}
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if (Icache.cacheAvail(in_msg.LineAddress)) {
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// L0-I does't have the line, but we have space for it
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// in the L0-I so let's see if the L1 has it
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trigger(prefetch_request_type_to_event(in_msg.Type),
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in_msg.LineAddress,
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icache_entry, TBEs[in_msg.LineAddress]);
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} else {
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// No room in the L0-I, so we need to make room in the L0-I
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Addr addr := Icache.cacheProbe(in_msg.LineAddress);
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check_on_cache_probe(optionalQueue_in, addr);
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trigger(Event:PF_L0_Replacement, addr,
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getICacheEntry(addr),
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TBEs[addr]);
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}
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} else {
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// Data prefetch
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Entry cache_entry := getDCacheEntry(in_msg.LineAddress);
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if (is_valid(cache_entry)) {
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// The block to be prefetched is already present in the
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// cache. This request will be made benign and cause the
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// prefetch queue to be popped.
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trigger(prefetch_request_type_to_event(in_msg.Type),
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in_msg.LineAddress,
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cache_entry, TBEs[in_msg.LineAddress]);
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}
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// Check to see if it is in the L0-I
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Entry icache_entry := getICacheEntry(in_msg.LineAddress);
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if (is_valid(icache_entry)) {
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// The block is in the wrong L0. Just drop the prefetch
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// request.
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trigger(prefetch_request_type_to_event(in_msg.Type),
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in_msg.LineAddress,
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icache_entry, TBEs[in_msg.LineAddress]);
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}
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if (Dcache.cacheAvail(in_msg.LineAddress)) {
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// L0-D does't have the line, but we have space for it in
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// the L0-D let's see if the L1 has it
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trigger(prefetch_request_type_to_event(in_msg.Type),
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in_msg.LineAddress,
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cache_entry, TBEs[in_msg.LineAddress]);
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} else {
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// No room in the L0-D, so we need to make room in the L0-D
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Addr addr := Dcache.cacheProbe(in_msg.LineAddress);
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check_on_cache_probe(optionalQueue_in, addr);
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trigger(Event:PF_L0_Replacement, addr,
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getDCacheEntry(addr),
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TBEs[addr]);
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}
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}
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}
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}
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}
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// Messages for this L0 cache from the L1 cache
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in_port(messgeBuffer_in, CoherenceMsg, bufferFromL1, rank = 1) {
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if (messgeBuffer_in.isReady(clockEdge())) {
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peek(messgeBuffer_in, CoherenceMsg, block_on="addr") {
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assert(in_msg.Dest == machineID);
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Entry cache_entry := getCacheEntry(in_msg.addr);
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TBE tbe := TBEs[in_msg.addr];
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if(in_msg.Class == CoherenceClass:DATA_EXCLUSIVE) {
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trigger(Event:Data_Exclusive, in_msg.addr, cache_entry, tbe);
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} else if(in_msg.Class == CoherenceClass:DATA) {
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trigger(Event:Data, in_msg.addr, cache_entry, tbe);
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} else if(in_msg.Class == CoherenceClass:STALE_DATA) {
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trigger(Event:Data_Stale, in_msg.addr, cache_entry, tbe);
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} else if (in_msg.Class == CoherenceClass:ACK) {
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trigger(Event:Ack, in_msg.addr, cache_entry, tbe);
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} else if (in_msg.Class == CoherenceClass:WB_ACK) {
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trigger(Event:WB_Ack, in_msg.addr, cache_entry, tbe);
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} else if (in_msg.Class == CoherenceClass:INV_OWN) {
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trigger(Event:InvOwn, in_msg.addr, cache_entry, tbe);
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} else if (in_msg.Class == CoherenceClass:INV_ELSE) {
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trigger(Event:InvElse, in_msg.addr, cache_entry, tbe);
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} else if (in_msg.Class == CoherenceClass:GETX ||
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in_msg.Class == CoherenceClass:UPGRADE) {
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// upgrade transforms to GETX due to race
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trigger(Event:Fwd_GETX, in_msg.addr, cache_entry, tbe);
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} else if (in_msg.Class == CoherenceClass:GETS) {
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trigger(Event:Fwd_GETS, in_msg.addr, cache_entry, tbe);
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} else if (in_msg.Class == CoherenceClass:GET_INSTR) {
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trigger(Event:Fwd_GET_INSTR, in_msg.addr, cache_entry, tbe);
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} else {
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error("Invalid forwarded request type");
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}
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}
|
|
}
|
|
}
|
|
|
|
// Mandatory Queue betweens Node's CPU and it's L0 caches
|
|
in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank = 0) {
|
|
if (mandatoryQueue_in.isReady(clockEdge())) {
|
|
peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
|
|
|
|
// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
|
|
|
|
if (in_msg.Type == RubyRequestType:IFETCH) {
|
|
// ** INSTRUCTION ACCESS ***
|
|
|
|
Entry Icache_entry := getICacheEntry(in_msg.LineAddress);
|
|
if (is_valid(Icache_entry)) {
|
|
// The tag matches for the L0, so the L0 asks the L2 for it.
|
|
trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
|
|
Icache_entry, TBEs[in_msg.LineAddress]);
|
|
} else {
|
|
|
|
// Check to see if it is in the OTHER L0
|
|
Entry Dcache_entry := getDCacheEntry(in_msg.LineAddress);
|
|
if (is_valid(Dcache_entry)) {
|
|
// The block is in the wrong L0, put the request on the queue to the shared L2
|
|
trigger(Event:L0_Replacement, in_msg.LineAddress,
|
|
Dcache_entry, TBEs[in_msg.LineAddress]);
|
|
}
|
|
|
|
if (Icache.cacheAvail(in_msg.LineAddress)) {
|
|
// L0 does't have the line, but we have space for it
|
|
// in the L0 so let's see if the L2 has it
|
|
trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
|
|
Icache_entry, TBEs[in_msg.LineAddress]);
|
|
} else {
|
|
// No room in the L0, so we need to make room in the L0
|
|
// Check if the line we want to evict is not locked
|
|
Addr addr := Icache.cacheProbe(in_msg.LineAddress);
|
|
check_on_cache_probe(mandatoryQueue_in, addr);
|
|
trigger(Event:L0_Replacement, addr,
|
|
getICacheEntry(addr),
|
|
TBEs[addr]);
|
|
}
|
|
}
|
|
} else {
|
|
// *** DATA ACCESS ***
|
|
Entry Dcache_entry := getDCacheEntry(in_msg.LineAddress);
|
|
|
|
// early out for failed store conditionals
|
|
|
|
if (in_msg.Type == RubyRequestType:Store_Conditional) {
|
|
if (!sequencer.llscCheckMonitor(in_msg.LineAddress)) {
|
|
trigger(Event:Failed_SC, in_msg.LineAddress,
|
|
Dcache_entry, TBEs[in_msg.LineAddress]);
|
|
}
|
|
}
|
|
|
|
if (is_valid(Dcache_entry)) {
|
|
// The tag matches for the L0, so the L0 ask the L1 for it
|
|
trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
|
|
Dcache_entry, TBEs[in_msg.LineAddress]);
|
|
} else {
|
|
// if the request is not valid, the store conditional will fail
|
|
if (in_msg.Type == RubyRequestType:Store_Conditional) {
|
|
// if the line is not valid, it can't be locked
|
|
trigger(Event:Failed_SC, in_msg.LineAddress,
|
|
Dcache_entry, TBEs[in_msg.LineAddress]);
|
|
} else {
|
|
// Check to see if it is in the OTHER L0
|
|
Entry Icache_entry := getICacheEntry(in_msg.LineAddress);
|
|
if (is_valid(Icache_entry)) {
|
|
// The block is in the wrong L0, put the request on the queue to the private L1
|
|
trigger(Event:L0_Replacement, in_msg.LineAddress,
|
|
Icache_entry, TBEs[in_msg.LineAddress]);
|
|
}
|
|
|
|
if (Dcache.cacheAvail(in_msg.LineAddress)) {
|
|
// L1 does't have the line, but we have space for it
|
|
// in the L0 let's see if the L1 has it
|
|
trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
|
|
Dcache_entry, TBEs[in_msg.LineAddress]);
|
|
} else {
|
|
// No room in the L1, so we need to make room in the L0
|
|
// Check if the line we want to evict is not locked
|
|
Addr addr := Dcache.cacheProbe(in_msg.LineAddress);
|
|
check_on_cache_probe(mandatoryQueue_in, addr);
|
|
trigger(Event:L0_Replacement, addr,
|
|
getDCacheEntry(addr),
|
|
TBEs[addr]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// ACTIONS
|
|
action(a_issueGETS, "a", desc="Issue GETS") {
|
|
peek(mandatoryQueue_in, RubyRequest) {
|
|
enqueue(requestNetwork_out, CoherenceMsg, request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Class := CoherenceClass:GETS;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
|
|
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
|
|
address, out_msg.Dest);
|
|
out_msg.MessageSize := MessageSizeType:Control;
|
|
out_msg.AccessMode := in_msg.AccessMode;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(b_issueGETX, "b", desc="Issue GETX") {
|
|
peek(mandatoryQueue_in, RubyRequest) {
|
|
enqueue(requestNetwork_out, CoherenceMsg, request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Class := CoherenceClass:GETX;
|
|
out_msg.Sender := machineID;
|
|
DPRINTF(RubySlicc, "%s\n", machineID);
|
|
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
|
|
|
|
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
|
|
address, out_msg.Dest);
|
|
out_msg.MessageSize := MessageSizeType:Control;
|
|
out_msg.AccessMode := in_msg.AccessMode;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(c_issueUPGRADE, "c", desc="Issue GETX") {
|
|
peek(mandatoryQueue_in, RubyRequest) {
|
|
enqueue(requestNetwork_out, CoherenceMsg, request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Class := CoherenceClass:UPGRADE;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
|
|
|
|
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
|
|
address, out_msg.Dest);
|
|
out_msg.MessageSize := MessageSizeType:Control;
|
|
out_msg.AccessMode := in_msg.AccessMode;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(f_sendDataToL1, "f", desc="Send data to the L1 cache") {
|
|
enqueue(requestNetwork_out, CoherenceMsg, response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.addr := address;
|
|
out_msg.Class := CoherenceClass:INV_DATA;
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Data;
|
|
}
|
|
cache_entry.Dirty := false;
|
|
}
|
|
|
|
action(fi_sendInvAck, "fi", desc="Send data to the L1 cache") {
|
|
peek(messgeBuffer_in, CoherenceMsg) {
|
|
enqueue(requestNetwork_out, CoherenceMsg, response_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Class := CoherenceClass:INV_ACK;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(forward_eviction_to_cpu, "\cc", desc="Send eviction information to the processor") {
|
|
if (send_evictions) {
|
|
DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
|
|
sequencer.evictionCallback(address);
|
|
}
|
|
}
|
|
|
|
action(g_issuePUTX, "g", desc="Relinquish line to the L1 cache") {
|
|
enqueue(requestNetwork_out, CoherenceMsg, response_latency) {
|
|
assert(is_valid(cache_entry));
|
|
out_msg.addr := address;
|
|
out_msg.Class := CoherenceClass:PUTX;
|
|
out_msg.Dirty := cache_entry.Dirty;
|
|
out_msg.Sender:= machineID;
|
|
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
|
|
|
|
if (cache_entry.Dirty) {
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Data;
|
|
out_msg.DataBlk := cache_entry.DataBlk;
|
|
} else {
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(h_load_hit, "hd", desc="Notify sequencer the load completed (cache hit)") {
|
|
assert(is_valid(cache_entry));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
Dcache.setMRU(cache_entry);
|
|
sequencer.readCallback(address, cache_entry.DataBlk);
|
|
}
|
|
|
|
action(h_ifetch_hit, "hi", desc="Notify sequencer the ifetch completed (cache hit)") {
|
|
assert(is_valid(cache_entry));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
Icache.setMRU(cache_entry);
|
|
sequencer.readCallback(address, cache_entry.DataBlk);
|
|
}
|
|
|
|
// The action name uses a counterintuitive _hit prefix when it is only
|
|
// called due to a cache miss. It is technically now a hit after having
|
|
// serviced the miss.
|
|
action(hx_load_hit, "hxd", desc="Notify sequencer the load completed (cache miss)") {
|
|
assert(is_valid(cache_entry));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
Dcache.setMRU(cache_entry);
|
|
sequencer.readCallback(address, cache_entry.DataBlk, true);
|
|
}
|
|
|
|
// The action name uses a counterintuitive _hit prefix when it is only
|
|
// called due to a cache miss. It is technically now a hit after having
|
|
// serviced the miss.
|
|
action(hx_ifetch_hit, "hxi", desc="Notify sequencer the ifetch completed (cache miss)") {
|
|
assert(is_valid(cache_entry));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
Icache.setMRU(cache_entry);
|
|
sequencer.readCallback(address, cache_entry.DataBlk, true);
|
|
}
|
|
|
|
action(hh_store_hit, "\h", desc="Notify sequencer that store completed (cache hit)") {
|
|
assert(is_valid(cache_entry));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
Dcache.setMRU(cache_entry);
|
|
sequencer.writeCallback(address, cache_entry.DataBlk);
|
|
cache_entry.Dirty := true;
|
|
}
|
|
|
|
// The action name uses a counterintuitive _hit prefix when it is only
|
|
// called due to a cache miss. It is technically now a hit after having
|
|
// serviced the miss.
|
|
action(hhx_store_hit, "\hx", desc="Notify sequencer that store completed (cache miss)") {
|
|
assert(is_valid(cache_entry));
|
|
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
|
|
Dcache.setMRU(cache_entry);
|
|
sequencer.writeCallback(address, cache_entry.DataBlk, true);
|
|
cache_entry.Dirty := true;
|
|
}
|
|
|
|
action(i_allocateTBE, "i", desc="Allocate TBE (number of invalidates=0)") {
|
|
check_allocate(TBEs);
|
|
assert(is_valid(cache_entry));
|
|
TBEs.allocate(address);
|
|
set_tbe(TBEs[address]);
|
|
tbe.Dirty := cache_entry.Dirty;
|
|
tbe.DataBlk := cache_entry.DataBlk;
|
|
}
|
|
|
|
action(k_popMandatoryQueue, "k", desc="Pop mandatory queue") {
|
|
mandatoryQueue_in.dequeue(clockEdge());
|
|
}
|
|
|
|
action(l_popRequestQueue, "l",
|
|
desc="Pop incoming request queue and profile the delay within this virtual network") {
|
|
Tick delay := messgeBuffer_in.dequeue(clockEdge());
|
|
profileMsgDelay(2, ticksToCycles(delay));
|
|
}
|
|
|
|
action(o_popIncomingResponseQueue, "o",
|
|
desc="Pop Incoming Response queue and profile the delay within this virtual network") {
|
|
Tick delay := messgeBuffer_in.dequeue(clockEdge());
|
|
profileMsgDelay(1, ticksToCycles(delay));
|
|
}
|
|
|
|
action(s_deallocateTBE, "s", desc="Deallocate TBE") {
|
|
TBEs.deallocate(address);
|
|
unset_tbe();
|
|
}
|
|
|
|
action(u_writeDataToCache, "u", desc="Write data to cache") {
|
|
peek(messgeBuffer_in, CoherenceMsg) {
|
|
assert(is_valid(cache_entry));
|
|
cache_entry.DataBlk := in_msg.DataBlk;
|
|
}
|
|
}
|
|
|
|
action(u_writeInstToCache, "ui", desc="Write data to cache") {
|
|
peek(messgeBuffer_in, CoherenceMsg) {
|
|
assert(is_valid(cache_entry));
|
|
cache_entry.DataBlk := in_msg.DataBlk;
|
|
}
|
|
}
|
|
|
|
action(ff_deallocateCacheBlock, "\f",
|
|
desc="Deallocate L1 cache block.") {
|
|
if (Dcache.isTagPresent(address)) {
|
|
Dcache.deallocate(address);
|
|
} else {
|
|
Icache.deallocate(address);
|
|
}
|
|
unset_cache_entry();
|
|
}
|
|
|
|
action(oo_allocateDCacheBlock, "\o", desc="Set L1 D-cache tag equal to tag of block B") {
|
|
if (is_invalid(cache_entry)) {
|
|
set_cache_entry(Dcache.allocate(address, new Entry));
|
|
}
|
|
}
|
|
|
|
action(pp_allocateICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B") {
|
|
if (is_invalid(cache_entry)) {
|
|
set_cache_entry(Icache.allocate(address, new Entry));
|
|
}
|
|
}
|
|
|
|
action(z_stallAndWaitMandatoryQueue, "\z", desc="Stall cpu request queue") {
|
|
stall_and_wait(mandatoryQueue_in, address);
|
|
}
|
|
|
|
action(kd_wakeUpDependents, "kd", desc="Wake-up dependents") {
|
|
wakeUpAllBuffers(address);
|
|
}
|
|
|
|
action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") {
|
|
Icache.profileDemandMiss();
|
|
}
|
|
|
|
action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
|
|
Icache.profileDemandHit();
|
|
}
|
|
|
|
action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") {
|
|
Dcache.profileDemandMiss();
|
|
}
|
|
|
|
action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
|
|
Dcache.profileDemandHit();
|
|
}
|
|
|
|
// store conditionals
|
|
|
|
action(hhc_storec_fail, "\hc",
|
|
desc="Notify sequencer that store conditional failed") {
|
|
sequencer.writeCallbackScFail(address, cache_entry.DataBlk);
|
|
}
|
|
|
|
// prefetching
|
|
|
|
action(pa_issuePfGETS, "pa", desc="Issue prefetch GETS") {
|
|
peek(optionalQueue_in, RubyRequest) {
|
|
enqueue(requestNetwork_out, CoherenceMsg, request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Class := CoherenceClass:GETS;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
|
|
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
|
|
address, out_msg.Dest);
|
|
out_msg.MessageSize := MessageSizeType:Control;
|
|
out_msg.Prefetch := in_msg.Prefetch;
|
|
out_msg.AccessMode := in_msg.AccessMode;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(pb_issuePfGETX, "pb", desc="Issue prefetch GETX") {
|
|
peek(optionalQueue_in, RubyRequest) {
|
|
enqueue(requestNetwork_out, CoherenceMsg, request_latency) {
|
|
out_msg.addr := address;
|
|
out_msg.Class := CoherenceClass:GETX;
|
|
out_msg.Sender := machineID;
|
|
DPRINTF(RubySlicc, "%s\n", machineID);
|
|
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
|
|
|
|
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
|
|
address, out_msg.Dest);
|
|
out_msg.MessageSize := MessageSizeType:Control;
|
|
out_msg.Prefetch := in_msg.Prefetch;
|
|
out_msg.AccessMode := in_msg.AccessMode;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(pq_popPrefetchQueue, "\pq", desc="Pop the prefetch request queue") {
|
|
optionalQueue_in.dequeue(clockEdge());
|
|
}
|
|
|
|
action(mp_markPrefetched, "mp", desc="Write data from response queue to cache") {
|
|
assert(is_valid(cache_entry));
|
|
cache_entry.isPrefetched := true;
|
|
}
|
|
|
|
action(po_observeMiss, "\po", desc="Inform the prefetcher about a cache miss") {
|
|
peek(mandatoryQueue_in, RubyRequest) {
|
|
if (enable_prefetch) {
|
|
prefetcher.observeMiss(in_msg.LineAddress, in_msg.Type);
|
|
}
|
|
}
|
|
}
|
|
|
|
action(ppm_observePfMiss, "\ppm",
|
|
desc="Inform the prefetcher about a cache miss with in-flight prefetch") {
|
|
peek(mandatoryQueue_in, RubyRequest) {
|
|
prefetcher.observePfMiss(in_msg.LineAddress);
|
|
}
|
|
}
|
|
|
|
action(pph_observePfHit, "\pph",
|
|
desc="Inform the prefetcher if a cache hit was the result of a prefetch") {
|
|
peek(mandatoryQueue_in, RubyRequest) {
|
|
if (cache_entry.isPrefetched) {
|
|
prefetcher.observePfHit(in_msg.LineAddress);
|
|
cache_entry.isPrefetched := false;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(z_stallAndWaitOptionalQueue, "\pz", desc="recycle prefetch request queue") {
|
|
stall_and_wait(optionalQueue_in, address);
|
|
}
|
|
|
|
//*****************************************************
|
|
// TRANSITIONS
|
|
//*****************************************************
|
|
|
|
// Transitions for Load/Store/Replacement/WriteBack from transient states
|
|
transition({Inst_IS, IS, IM, SM}, {Load, Ifetch, Store, L0_Replacement}) {
|
|
z_stallAndWaitMandatoryQueue;
|
|
}
|
|
|
|
// Transitions from Idle
|
|
transition(I, Load, IS) {
|
|
oo_allocateDCacheBlock;
|
|
i_allocateTBE;
|
|
a_issueGETS;
|
|
uu_profileDataMiss;
|
|
po_observeMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(I, Ifetch, Inst_IS) {
|
|
pp_allocateICacheBlock;
|
|
i_allocateTBE;
|
|
a_issueGETS;
|
|
uu_profileInstMiss;
|
|
po_observeMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(I, Store, IM) {
|
|
oo_allocateDCacheBlock;
|
|
i_allocateTBE;
|
|
b_issueGETX;
|
|
uu_profileDataMiss;
|
|
po_observeMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({I, IS, IM, Inst_IS}, {InvOwn, InvElse}) {
|
|
forward_eviction_to_cpu;
|
|
fi_sendInvAck;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(SM, {InvOwn, InvElse}, IM) {
|
|
forward_eviction_to_cpu;
|
|
fi_sendInvAck;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
// Transitions from Shared
|
|
transition({S,E,M}, Load) {
|
|
h_load_hit;
|
|
uu_profileDataHit;
|
|
pph_observePfHit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({S,E,M}, Ifetch) {
|
|
h_ifetch_hit;
|
|
uu_profileInstHit;
|
|
pph_observePfHit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(S, Store, SM) {
|
|
i_allocateTBE;
|
|
c_issueUPGRADE;
|
|
uu_profileDataMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(S, {L0_Replacement,PF_L0_Replacement}, I) {
|
|
forward_eviction_to_cpu;
|
|
ff_deallocateCacheBlock;
|
|
}
|
|
|
|
transition(S, {InvOwn, InvElse}, I) {
|
|
forward_eviction_to_cpu;
|
|
fi_sendInvAck;
|
|
ff_deallocateCacheBlock;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
// Transitions from Exclusive
|
|
transition({E,M}, Store, M) {
|
|
hh_store_hit;
|
|
uu_profileDataHit;
|
|
pph_observePfHit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(E, {L0_Replacement,PF_L0_Replacement}, I) {
|
|
forward_eviction_to_cpu;
|
|
g_issuePUTX;
|
|
ff_deallocateCacheBlock;
|
|
}
|
|
|
|
transition(E, {InvOwn, InvElse, Fwd_GETX}, I) {
|
|
// don't send data
|
|
forward_eviction_to_cpu;
|
|
fi_sendInvAck;
|
|
ff_deallocateCacheBlock;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(E, {Fwd_GETS, Fwd_GET_INSTR}, S) {
|
|
f_sendDataToL1;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
// Transitions from Modified
|
|
transition(M, {L0_Replacement,PF_L0_Replacement}, I) {
|
|
forward_eviction_to_cpu;
|
|
g_issuePUTX;
|
|
ff_deallocateCacheBlock;
|
|
}
|
|
|
|
transition(M, {InvOwn, InvElse, Fwd_GETX}, I) {
|
|
forward_eviction_to_cpu;
|
|
f_sendDataToL1;
|
|
ff_deallocateCacheBlock;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(M, {Fwd_GETS, Fwd_GET_INSTR}, S) {
|
|
f_sendDataToL1;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(IS, Data, S) {
|
|
u_writeDataToCache;
|
|
hx_load_hit;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(IS, Data_Exclusive, E) {
|
|
u_writeDataToCache;
|
|
hx_load_hit;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(IS, Data_Stale, I) {
|
|
u_writeDataToCache;
|
|
forward_eviction_to_cpu;
|
|
hx_load_hit;
|
|
s_deallocateTBE;
|
|
ff_deallocateCacheBlock;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(Inst_IS, Data, S) {
|
|
u_writeInstToCache;
|
|
hx_ifetch_hit;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(Inst_IS, Data_Exclusive, E) {
|
|
u_writeInstToCache;
|
|
hx_ifetch_hit;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(Inst_IS, Data_Stale, I) {
|
|
u_writeInstToCache;
|
|
hx_ifetch_hit;
|
|
s_deallocateTBE;
|
|
ff_deallocateCacheBlock;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition({IM,SM}, Data_Exclusive, M) {
|
|
u_writeDataToCache;
|
|
hhx_store_hit;
|
|
s_deallocateTBE;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
// store conditionals
|
|
|
|
transition({I,S,E,M}, Failed_SC) {
|
|
// IS,IM,SM don't handle store conditionals
|
|
hhc_storec_fail;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
// prefetcher
|
|
|
|
transition({Inst_IS, IS, IM, SM, PF_Inst_IS, PF_IS, PF_IE}, PF_L0_Replacement) {
|
|
z_stallAndWaitOptionalQueue;
|
|
}
|
|
|
|
transition({PF_Inst_IS, PF_IS}, {Store, L0_Replacement}) {
|
|
z_stallAndWaitMandatoryQueue;
|
|
}
|
|
|
|
transition({PF_IE}, {Load, Ifetch, L0_Replacement}) {
|
|
z_stallAndWaitMandatoryQueue;
|
|
}
|
|
|
|
transition({S,E,M,Inst_IS,IS,IM,SM,PF_Inst_IS,PF_IS,PF_IE},
|
|
{PF_Load, PF_Store, PF_Ifetch}) {
|
|
pq_popPrefetchQueue;
|
|
}
|
|
|
|
transition(I, PF_Load, PF_IS) {
|
|
oo_allocateDCacheBlock;
|
|
i_allocateTBE;
|
|
pa_issuePfGETS;
|
|
pq_popPrefetchQueue;
|
|
}
|
|
|
|
transition(PF_IS, Load, IS) {
|
|
uu_profileDataMiss;
|
|
ppm_observePfMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(I, PF_Ifetch, PF_Inst_IS) {
|
|
pp_allocateICacheBlock;
|
|
i_allocateTBE;
|
|
pa_issuePfGETS;
|
|
pq_popPrefetchQueue;
|
|
}
|
|
|
|
transition(PF_Inst_IS, Ifetch, Inst_IS) {
|
|
uu_profileInstMiss;
|
|
ppm_observePfMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(I, PF_Store, PF_IE) {
|
|
oo_allocateDCacheBlock;
|
|
i_allocateTBE;
|
|
pb_issuePfGETX;
|
|
pq_popPrefetchQueue;
|
|
}
|
|
|
|
transition(PF_IE, Store, IM) {
|
|
uu_profileDataMiss;
|
|
ppm_observePfMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({PF_Inst_IS, PF_IS, PF_IE}, {InvOwn, InvElse}) {
|
|
fi_sendInvAck;
|
|
l_popRequestQueue;
|
|
}
|
|
|
|
transition(PF_IS, Data, S) {
|
|
u_writeDataToCache;
|
|
s_deallocateTBE;
|
|
mp_markPrefetched;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(PF_IS, Data_Exclusive, E) {
|
|
u_writeDataToCache;
|
|
s_deallocateTBE;
|
|
mp_markPrefetched;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(PF_IS, Data_Stale, I) {
|
|
u_writeDataToCache;
|
|
s_deallocateTBE;
|
|
mp_markPrefetched;
|
|
ff_deallocateCacheBlock;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(PF_Inst_IS, Data, S) {
|
|
u_writeInstToCache;
|
|
s_deallocateTBE;
|
|
mp_markPrefetched;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(PF_Inst_IS, Data_Exclusive, E) {
|
|
u_writeInstToCache;
|
|
s_deallocateTBE;
|
|
mp_markPrefetched;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(PF_IE, Data_Exclusive, E) {
|
|
u_writeDataToCache;
|
|
s_deallocateTBE;
|
|
mp_markPrefetched;
|
|
o_popIncomingResponseQueue;
|
|
kd_wakeUpDependents;
|
|
}
|
|
|
|
transition(I, PF_Bad_Addr) {
|
|
pq_popPrefetchQueue;
|
|
}
|
|
}
|