d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
80 lines
3.3 KiB
Python
80 lines
3.3 KiB
Python
# Copyright (c) 2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.citations import add_citation
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from m5.objects.AbstractMemory import *
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from m5.params import *
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# A wrapper for DRAMSim3 multi-channel memory controller
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class DRAMsim3(AbstractMemory):
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type = "DRAMsim3"
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cxx_header = "mem/dramsim3.hh"
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cxx_class = "gem5::memory::DRAMsim3"
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# A single port for now
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port = ResponsePort(
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"port for receiving requests fromthe CPU or other requestor"
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)
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configFile = Param.String(
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"ext/dramsim3/DRAMsim3/configs/DDR4_8Gb_x8_2400.ini",
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"The configuration file to use with DRAMSim3",
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)
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filePath = Param.String(
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"ext/dramsim3/DRAMsim3/", "Directory to prepend to file names"
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)
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add_citation(
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DRAMsim3,
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"""@article{Li:2020:dramsim3,
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author = {Shang Li and
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Zhiyuan Yang and
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Dhiraj Reddy and
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Ankur Srivastava and
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Bruce L. Jacob},
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title = {DRAMsim3: {A} Cycle-Accurate, Thermal-Capable {DRAM} Simulator},
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journal = {{IEEE} Compututer Architecture Letters},
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volume = {19},
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number = {2},
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pages = {110--113},
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year = {2020},
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url = {https://doi.org/10.1109/LCA.2020.2973991},
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doi = {10.1109/LCA.2020.2973991}
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}
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""",
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)
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