d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
118 lines
5.2 KiB
Python
118 lines
5.2 KiB
Python
# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects.System import System
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from m5.params import *
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from m5.proxy import *
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from m5.SimObject import SimObject
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# The communication monitor will most typically be used in combination
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# with periodic dumping and resetting of stats using schedStatEvent
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class CommMonitor(SimObject):
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type = "CommMonitor"
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cxx_header = "mem/comm_monitor.hh"
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cxx_class = "gem5::CommMonitor"
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system = Param.System(Parent.any, "System that the monitor belongs to.")
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# one port in each direction
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mem_side_port = RequestPort(
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"This port sends requests and receives responses"
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)
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master = DeprecatedParam(
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mem_side_port, "`master` is now called `mem_side_port`"
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)
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cpu_side_port = ResponsePort(
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"This port receives requests and sends responses"
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)
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slave = DeprecatedParam(
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cpu_side_port, "`slave` is now called `cpu_side_port`"
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)
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# control the sample period window length of this monitor
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sample_period = Param.Clock("1ms", "Sample period for histograms")
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# for each histogram, set the number of bins and enable the user
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# to disable the measurement, reads and writes use the same
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# parameters
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# histogram of burst length of packets (not using sample period)
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burst_length_bins = Param.Unsigned(
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"20", "# bins in burst length histograms"
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)
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disable_burst_length_hists = Param.Bool(
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False, "Disable burst length histograms"
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)
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# bandwidth per sample period
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bandwidth_bins = Param.Unsigned("20", "# bins in bandwidth histograms")
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disable_bandwidth_hists = Param.Bool(False, "Disable bandwidth histograms")
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# latency from request to response (not using sample period)
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latency_bins = Param.Unsigned("20", "# bins in latency histograms")
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disable_latency_hists = Param.Bool(False, "Disable latency histograms")
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# inter transaction time (ITT) distributions in uniformly sized
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# bins up to the maximum, independently for read-to-read,
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# write-to-write and the combined request-to-request that does not
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# separate read and write requests
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itt_bins = Param.Unsigned("20", "# bins in ITT distributions")
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itt_max_bin = Param.Latency("100ns", "Max bin of ITT distributions")
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disable_itt_dists = Param.Bool(False, "Disable ITT distributions")
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# outstanding requests (that did not yet get a response) per
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# sample period
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outstanding_bins = Param.Unsigned(
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"20", "# bins in outstanding requests histograms"
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)
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disable_outstanding_hists = Param.Bool(
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False, "Disable outstanding requests histograms"
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)
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# transactions (requests) observed per sample period
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transaction_bins = Param.Unsigned(
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"20", "# bins in transaction count histograms"
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)
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disable_transaction_hists = Param.Bool(
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False, "Disable transaction count histograms"
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)
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# address distributions (heatmaps) with associated address masks
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# to selectively only look at certain bits of the address
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read_addr_mask = Param.Addr(MaxAddr, "Address mask for read address")
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write_addr_mask = Param.Addr(MaxAddr, "Address mask for write address")
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disable_addr_dists = Param.Bool(True, "Disable address distributions")
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