8759131df3
This PR is fixing https://github.com/gem5/gem5/issues/668. It fixes it for all ISAs other than Arm with the first commit, which is setting the number of architectural Matrix registers to 0 for those ISA which are not using them. It then partly fixes it for Arm as well with the 2nd commit: by removing RenameMap::numFreeEntries we don't stall renaming unless a matrix instruction is encountered... This means most binaries will run with SMT as long as they don't use FEAT_SME instructions. Please note: this is not simply a SMT fix, it will generally address a shortcoming in the way we were renaming instructions. If an Arm binary wants to use SMT with FEAT_SME, the 4th commit will make sure the lack of physical registers is notified explicitly at the beginning of simulation, rather than silently blocking renaming
298 lines
10 KiB
C++
298 lines
10 KiB
C++
/*
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* Copyright (c) 2015-2017 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_RENAME_MAP_HH__
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#define __CPU_O3_RENAME_MAP_HH__
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#include <algorithm>
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#include <array>
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#include <iostream>
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#include <limits>
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#include <utility>
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#include <vector>
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#include "arch/generic/isa.hh"
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#include "cpu/o3/dyn_inst_ptr.hh"
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#include "cpu/o3/free_list.hh"
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#include "cpu/o3/regfile.hh"
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#include "cpu/reg_class.hh"
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namespace gem5
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{
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namespace o3
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{
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/**
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* Register rename map for a single class of registers (e.g., integer
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* or floating point). Because the register class is implicitly
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* determined by the rename map instance being accessed, all
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* architectural register index parameters and values in this class
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* are relative (e.g., %fp2 is just index 2).
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*/
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class SimpleRenameMap
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{
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private:
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using Arch2PhysMap = std::vector<PhysRegIdPtr>;
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/** The acutal arch-to-phys register map */
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Arch2PhysMap map;
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public:
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using iterator = Arch2PhysMap::iterator;
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using const_iterator = Arch2PhysMap::const_iterator;
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private:
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/**
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* Pointer to the free list from which new physical registers
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* should be allocated in rename()
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*/
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SimpleFreeList *freeList;
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public:
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SimpleRenameMap();
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/**
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* Because we have an array of rename maps (one per thread) in the CPU,
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* it's awkward to initialize this object via the constructor.
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* Instead, this method is used for initialization.
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*/
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void init(const RegClass ®_class, SimpleFreeList *_freeList);
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/**
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* Pair of a physical register and a physical register. Used to
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* return the physical register that a logical register has been
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* renamed to, and the previous physical register that the same
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* logical register was previously mapped to.
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*/
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typedef std::pair<PhysRegIdPtr, PhysRegIdPtr> RenameInfo;
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/**
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* Tell rename map to get a new free physical register to remap
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* the specified architectural register.
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* @param arch_reg The architectural register to remap.
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* @return A RenameInfo pair indicating both the new and previous
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* physical registers.
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*/
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RenameInfo rename(const RegId& arch_reg);
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/**
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* Look up the physical register mapped to an architectural register.
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* @param arch_reg The architectural register to look up.
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* @return The physical register it is currently mapped to.
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*/
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PhysRegIdPtr
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lookup(const RegId& arch_reg) const
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{
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assert(arch_reg.index() <= map.size());
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return map[arch_reg.index()];
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}
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/**
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* Update rename map with a specific mapping. Generally used to
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* roll back to old mappings on a squash.
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* @param arch_reg The architectural register to remap.
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* @param phys_reg The physical register to remap it to.
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*/
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void
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setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
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{
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assert(arch_reg.index() <= map.size());
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map[arch_reg.index()] = phys_reg;
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}
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/** Return the number of free entries on the associated free list. */
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unsigned numFreeEntries() const { return freeList->numFreeRegs(); }
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size_t numArchRegs() const { return map.size(); }
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/** Forward begin/cbegin to the map. */
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/** @{ */
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iterator begin() { return map.begin(); }
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const_iterator begin() const { return map.begin(); }
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const_iterator cbegin() const { return map.cbegin(); }
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/** @} */
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/** Forward end/cend to the map. */
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/** @{ */
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iterator end() { return map.end(); }
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const_iterator end() const { return map.end(); }
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const_iterator cend() const { return map.cend(); }
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/** @} */
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};
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/**
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* Unified register rename map for all classes of registers. Wraps a
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* set of class-specific rename maps. Methods that do not specify a
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* register class (e.g., rename()) take register ids,
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* while methods that do specify a register class (e.g., renameInt())
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* take register indices.
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*/
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class UnifiedRenameMap
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{
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private:
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std::array<SimpleRenameMap, CCRegClass + 1> renameMaps;
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static inline PhysRegId invalidPhysRegId{};
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/**
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* The register file object is used only to get PhysRegIdPtr
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* on MiscRegs, as they are stored in it.
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*/
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PhysRegFile *regFile;
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public:
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typedef SimpleRenameMap::RenameInfo RenameInfo;
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typedef std::array<UnifiedRenameMap, MaxThreads> PerThreadUnifiedRenameMap;
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/** Default constructor. init() must be called prior to use. */
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UnifiedRenameMap() : regFile(nullptr) {};
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/** Destructor. */
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~UnifiedRenameMap() {};
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/** Initializes rename map with given parameters. */
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void init(const BaseISA::RegClasses ®Classes,
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PhysRegFile *_regFile, UnifiedFreeList *freeList);
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/**
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* Tell rename map to get a new free physical register to remap
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* the specified architectural register. This version takes a
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* RegId and reads the appropriate class-specific rename table.
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* @param arch_reg The architectural register id to remap.
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* @return A RenameInfo pair indicating both the new and previous
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* physical registers.
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*/
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RenameInfo
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rename(const RegId& arch_reg)
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{
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if (!arch_reg.isRenameable()) {
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// misc regs aren't really renamed, just remapped
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PhysRegIdPtr phys_reg = lookup(arch_reg);
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// Set the new register to the previous one to keep the same
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// mapping throughout the execution.
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return RenameInfo(phys_reg, phys_reg);
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}
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return renameMaps[arch_reg.classValue()].rename(arch_reg);
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}
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/**
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* Look up the physical register mapped to an architectural register.
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* This version takes a flattened architectural register id
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* and calls the appropriate class-specific rename table.
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* @param arch_reg The architectural register to look up.
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* @return The physical register it is currently mapped to.
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*/
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PhysRegIdPtr
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lookup(const RegId& arch_reg) const
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{
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auto reg_class = arch_reg.classValue();
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if (reg_class == InvalidRegClass) {
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return &invalidPhysRegId;
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} else if (reg_class == MiscRegClass) {
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// misc regs aren't really renamed, they keep the same
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// mapping throughout the execution.
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return regFile->getMiscRegId(arch_reg.index());
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}
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return renameMaps[reg_class].lookup(arch_reg);
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}
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/**
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* Update rename map with a specific mapping. Generally used to
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* roll back to old mappings on a squash. This version takes a
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* flattened architectural register id and calls the
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* appropriate class-specific rename table.
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* @param arch_reg The architectural register to remap.
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* @param phys_reg The physical register to remap it to.
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*/
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void
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setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
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{
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assert(phys_reg->is(arch_reg.classValue()));
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if (!arch_reg.isRenameable()) {
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// Misc registers do not actually rename, so don't change
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// their mappings. We end up here when a commit or squash
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// tries to update or undo a hardwired misc reg nmapping,
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// which should always be setting it to what it already is.
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assert(phys_reg == lookup(arch_reg));
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return;
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}
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return renameMaps[arch_reg.classValue()].setEntry(arch_reg, phys_reg);
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}
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/**
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* Return the minimum number of free entries across all of the
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* register classes. The minimum is used so we guarantee that
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* this number of entries is available regardless of which class
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* of registers is requested.
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*/
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unsigned
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minFreeEntries() const
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{
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auto min_free = std::numeric_limits<unsigned>::max();
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for (auto &map: renameMaps) {
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// If this map isn't empty (not used)...
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if (map.numArchRegs())
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min_free = std::min(min_free, map.numFreeEntries());
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}
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return min_free;
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}
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unsigned
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numFreeEntries(RegClassType type) const
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{
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return renameMaps[type].numFreeEntries();
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}
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/**
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* Return whether there are enough registers to serve the request.
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*/
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bool canRename(DynInstPtr inst) const;
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};
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} // namespace o3
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} // namespace gem5
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#endif //__CPU_O3_RENAME_MAP_HH__
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