d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
194 lines
7.7 KiB
Python
194 lines
7.7 KiB
Python
# Copyright (c) 2016, 2019 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.defines import buildEnv
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from m5.objects.BaseCPU import BaseCPU
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# from m5.objects.O3Checker import O3Checker
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from m5.objects.BranchPredictor import *
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from m5.objects.FUPool import *
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from m5.params import *
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from m5.proxy import *
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class SMTFetchPolicy(ScopedEnum):
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vals = ["RoundRobin", "Branch", "IQCount", "LSQCount"]
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class SMTQueuePolicy(ScopedEnum):
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vals = ["Dynamic", "Partitioned", "Threshold"]
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class CommitPolicy(ScopedEnum):
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vals = ["RoundRobin", "OldestReady"]
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class BaseO3CPU(BaseCPU):
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type = "BaseO3CPU"
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cxx_class = "gem5::o3::CPU"
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cxx_header = "cpu/o3/dyn_inst.hh"
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@classmethod
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def memory_mode(cls):
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return "timing"
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@classmethod
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def require_caches(cls):
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return True
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@classmethod
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def support_take_over(cls):
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return True
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activity = Param.Unsigned(0, "Initial count")
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cacheStorePorts = Param.Unsigned(
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200, "Cache Ports. Constrains stores only."
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)
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cacheLoadPorts = Param.Unsigned(200, "Cache Ports. Constrains loads only.")
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decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
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renameToFetchDelay = Param.Cycles(1, "Rename to fetch delay")
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iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch delay")
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commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
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fetchWidth = Param.Unsigned(8, "Fetch width")
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fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
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fetchQueueSize = Param.Unsigned(
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32, "Fetch queue size in micro-ops per-thread"
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)
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renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
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iewToDecodeDelay = Param.Cycles(
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1, "Issue/Execute/Writeback to decode delay"
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)
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commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
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fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
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decodeWidth = Param.Unsigned(8, "Decode width")
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iewToRenameDelay = Param.Cycles(
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1, "Issue/Execute/Writeback to rename delay"
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)
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commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
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decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
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renameWidth = Param.Unsigned(8, "Rename width")
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commitToIEWDelay = Param.Cycles(
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1, "Commit to Issue/Execute/Writeback delay"
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)
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renameToIEWDelay = Param.Cycles(
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2, "Rename to Issue/Execute/Writeback delay"
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)
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issueToExecuteDelay = Param.Cycles(
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1, "Issue to execute delay (internal to the IEW stage)"
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)
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dispatchWidth = Param.Unsigned(8, "Dispatch width")
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issueWidth = Param.Unsigned(8, "Issue width")
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wbWidth = Param.Unsigned(8, "Writeback width")
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fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
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iewToCommitDelay = Param.Cycles(
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1, "Issue/Execute/Writeback to commit delay"
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)
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renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
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commitWidth = Param.Unsigned(8, "Commit width")
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squashWidth = Param.Unsigned(8, "Squash width")
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trapLatency = Param.Cycles(13, "Trap latency")
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fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
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backComSize = Param.Unsigned(
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5, "Time buffer size for backwards communication"
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)
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forwardComSize = Param.Unsigned(
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5, "Time buffer size for forward communication"
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)
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LQEntries = Param.Unsigned(32, "Number of load queue entries")
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SQEntries = Param.Unsigned(32, "Number of store queue entries")
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LSQDepCheckShift = Param.Unsigned(
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4, "Number of places to shift addr before check"
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)
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LSQCheckLoads = Param.Bool(
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True,
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"Should dependency violations be checked for "
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"loads & stores or just stores",
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)
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store_set_clear_period = Param.Unsigned(
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250000,
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"Number of load/store insts before the dep predictor "
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"should be invalidated",
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)
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LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
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SSITSize = Param.Unsigned(1024, "Store set ID table size")
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numRobs = Param.Unsigned(1, "Number of Reorder Buffers")
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numPhysIntRegs = Param.Unsigned(
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256, "Number of physical integer registers"
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)
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numPhysFloatRegs = Param.Unsigned(
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256, "Number of physical floating point registers"
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)
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numPhysVecRegs = Param.Unsigned(256, "Number of physical vector registers")
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numPhysVecPredRegs = Param.Unsigned(
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32, "Number of physical predicate registers"
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)
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numPhysMatRegs = Param.Unsigned(2, "Number of physical matrix registers")
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# most ISAs don't use condition-code regs, so default is 0
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numPhysCCRegs = Param.Unsigned(0, "Number of physical cc registers")
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numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
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numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
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smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
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smtFetchPolicy = Param.SMTFetchPolicy("RoundRobin", "SMT Fetch policy")
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smtLSQPolicy = Param.SMTQueuePolicy(
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"Partitioned", "SMT LSQ Sharing Policy"
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)
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smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
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smtIQPolicy = Param.SMTQueuePolicy("Partitioned", "SMT IQ Sharing Policy")
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smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
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smtROBPolicy = Param.SMTQueuePolicy(
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"Partitioned", "SMT ROB Sharing Policy"
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)
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smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
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smtCommitPolicy = Param.CommitPolicy("RoundRobin", "SMT Commit Policy")
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branchPred = Param.BranchPredictor(
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TournamentBP(numThreads=Parent.numThreads), "Branch Predictor"
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)
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needsTSO = Param.Bool(False, "Enable TSO Memory model")
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