70f9a32117
This is no longer used. Change-Id: I0ec170fb3b450430bbeff0a3c37bcdafe70c92b0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52053 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Gabe Black <gabe.black@gmail.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
582 lines
13 KiB
C++
582 lines
13 KiB
C++
/*
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* Copyright (c) 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2010 Gabe Black
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_GENERIC_TYPES_HH__
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#define __ARCH_GENERIC_TYPES_HH__
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#include <iostream>
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#include <memory>
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#include <type_traits>
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#include "base/compiler.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "sim/serialize.hh"
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namespace gem5
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{
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// The guaranteed interface.
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class PCStateBase : public Serializable
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{
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protected:
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Addr _pc = 0;
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MicroPC _upc = 0;
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PCStateBase(const PCStateBase &other) : _pc(other._pc), _upc(other._upc) {}
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PCStateBase &operator=(const PCStateBase &other) = default;
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PCStateBase() {}
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public:
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virtual ~PCStateBase() = default;
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template<class Target>
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Target &
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as()
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{
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return static_cast<Target &>(*this);
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}
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template<class Target>
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const Target &
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as() const
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{
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return static_cast<const Target &>(*this);
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}
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virtual PCStateBase *clone() const = 0;
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virtual void
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update(const PCStateBase &other)
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{
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_pc = other._pc;
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_upc = other._upc;
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}
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void update(const PCStateBase *ptr) { update(*ptr); }
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virtual void output(std::ostream &os) const = 0;
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virtual bool
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equals(const PCStateBase &other) const
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{
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return _pc == other._pc && _upc == other._upc;
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}
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/**
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* Returns the memory address of the instruction this PC points to.
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*
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* @return Memory address of the instruction this PC points to.
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*/
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Addr
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instAddr() const
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{
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return _pc;
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}
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/**
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* Returns the current micropc.
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*
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* @return The current micropc.
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*/
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MicroPC
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microPC() const
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{
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return _upc;
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}
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void
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serialize(CheckpointOut &cp) const override
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{
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SERIALIZE_SCALAR(_pc);
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SERIALIZE_SCALAR(_upc);
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}
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void
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unserialize(CheckpointIn &cp) override
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{
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UNSERIALIZE_SCALAR(_pc);
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UNSERIALIZE_SCALAR(_upc);
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}
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};
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static inline std::ostream &
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operator<<(std::ostream & os, const PCStateBase &pc)
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{
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pc.output(os);
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return os;
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}
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static inline bool
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operator==(const PCStateBase &a, const PCStateBase &b)
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{
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return a.equals(b);
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}
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static inline bool
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operator!=(const PCStateBase &a, const PCStateBase &b)
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{
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return !a.equals(b);
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}
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namespace
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{
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inline void
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set(PCStateBase *&dest, const PCStateBase *src)
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{
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if (GEM5_LIKELY(dest)) {
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if (GEM5_LIKELY(src)) {
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// Both src and dest already have storage, so just copy contents.
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dest->update(src);
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} else {
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// src is empty, so clear out dest.
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dest = nullptr;
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}
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} else {
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if (GEM5_LIKELY(src)) {
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// dest doesn't have storage, so create some as a copy of src.
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dest = src->clone();
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} else {
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// dest is already nullptr, so nothing to do.
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}
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}
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}
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inline void
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set(std::unique_ptr<PCStateBase> &dest, const PCStateBase *src)
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{
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PCStateBase *dest_ptr = dest.get();
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set(dest_ptr, src);
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if (dest.get() != dest_ptr)
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dest.reset(dest_ptr);
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}
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inline void
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set(PCStateBase *&dest, const std::unique_ptr<PCStateBase> &src)
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{
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const PCStateBase *src_ptr = src.get();
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set(dest, src_ptr);
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}
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inline void
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set(std::unique_ptr<PCStateBase> &dest,
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const std::unique_ptr<PCStateBase> &src)
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{
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PCStateBase *dest_ptr = dest.get();
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const PCStateBase *src_ptr = src.get();
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set(dest_ptr, src_ptr);
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if (dest.get() != dest_ptr)
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dest.reset(dest_ptr);
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}
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inline void
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set(PCStateBase *&dest, const PCStateBase &src)
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{
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if (GEM5_LIKELY(dest)) {
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// Update dest with the contents of src.
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dest->update(src);
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} else {
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// Clone src over to dest.
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dest = src.clone();
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}
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}
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inline void
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set(std::unique_ptr<PCStateBase> &dest, const PCStateBase &src)
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{
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PCStateBase *dest_ptr = dest.get();
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set(dest_ptr, src);
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if (dest.get() != dest_ptr)
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dest.reset(dest_ptr);
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}
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inline void
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set(PCStateBase &dest, const PCStateBase &src)
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{
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dest.update(src);
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}
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} // anonymous namespace
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namespace GenericISA
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{
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class PCStateCommon : public PCStateBase
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{
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protected:
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Addr _npc = 0;
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MicroPC _nupc = 1;
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PCStateCommon(const PCStateCommon &other) : PCStateBase(other),
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_npc(other._npc), _nupc(other._nupc)
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{}
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PCStateCommon &operator=(const PCStateCommon &other) = default;
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PCStateCommon() {}
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public:
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Addr pc() const { return _pc; }
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void pc(Addr val) { _pc = val; }
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Addr npc() const { return _npc; }
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void npc(Addr val) { _npc = val; }
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MicroPC upc() const { return _upc; }
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void upc(MicroPC val) { _upc = val; }
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MicroPC nupc() const { return _nupc; }
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void nupc(MicroPC val) { _nupc = val; }
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// Reset the macroop's upc without advancing the regular pc.
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void
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uReset()
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{
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_upc = 0;
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_nupc = 1;
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}
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void
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setNPC(Addr val)
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{
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npc(val);
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}
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void
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output(std::ostream &os) const override
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{
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ccprintf(os, "(%#x=>%#x)", this->pc(), this->npc());
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}
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void
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update(const PCStateBase &other) override
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{
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PCStateBase::update(other);
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auto &pcstate = other.as<PCStateCommon>();
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_npc = pcstate._npc;
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_nupc = pcstate._nupc;
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}
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bool
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equals(const PCStateBase &other) const override
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{
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auto &ps = other.as<PCStateCommon>();
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return PCStateBase::equals(other) &&
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_npc == ps._npc && _nupc == ps._nupc;
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}
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void
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serialize(CheckpointOut &cp) const override
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{
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PCStateBase::serialize(cp);
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SERIALIZE_SCALAR(_npc);
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SERIALIZE_SCALAR(_nupc);
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}
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void
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unserialize(CheckpointIn &cp) override
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{
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PCStateBase::unserialize(cp);
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UNSERIALIZE_SCALAR(_npc);
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UNSERIALIZE_SCALAR(_nupc);
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}
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};
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/*
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* Different flavors of PC state. Only ISA specific code should rely on
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* any particular type of PC state being available. All other code should
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* use the interface above.
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*/
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// The most basic type of PC.
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template <int InstWidth>
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class SimplePCState : public PCStateCommon
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{
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protected:
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typedef PCStateCommon Base;
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public:
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SimplePCState(const SimplePCState &other) : Base(other) {}
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SimplePCState &operator=(const SimplePCState &other) = default;
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SimplePCState() {}
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explicit SimplePCState(Addr val) { set(val); }
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PCStateBase *
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clone() const override
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{
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return new SimplePCState<InstWidth>(*this);
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}
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/**
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* Force this PC to reflect a particular value, resetting all its other
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* fields around it. This is useful for in place (re)initialization.
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*
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* @param val The value to set the PC to.
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*/
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void
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set(Addr val)
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{
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this->pc(val);
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this->npc(val + InstWidth);
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};
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bool
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branching() const
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{
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return this->npc() != this->pc() + InstWidth;
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}
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// Advance the PC.
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void
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advance()
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{
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this->_pc = this->_npc;
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this->_npc += InstWidth;
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}
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};
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// A PC and microcode PC.
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template <int InstWidth>
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class UPCState : public SimplePCState<InstWidth>
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{
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protected:
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typedef SimplePCState<InstWidth> Base;
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public:
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void
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output(std::ostream &os) const override
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{
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Base::output(os);
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ccprintf(os, ".(%d=>%d)", this->upc(), this->nupc());
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}
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PCStateBase *
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clone() const override
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{
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return new UPCState<InstWidth>(*this);
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}
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void
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set(Addr val)
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{
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Base::set(val);
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this->upc(0);
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this->nupc(1);
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}
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UPCState(const UPCState &other) : Base(other) {}
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UPCState &operator=(const UPCState &other) = default;
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UPCState() {}
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explicit UPCState(Addr val) { set(val); }
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bool
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branching() const
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{
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return this->npc() != this->pc() + InstWidth ||
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this->nupc() != this->upc() + 1;
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}
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// Advance the upc within the instruction.
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void
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uAdvance()
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{
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this->upc(this->nupc());
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this->nupc(this->nupc() + 1);
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}
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// End the macroop by resetting the upc and advancing the regular pc.
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void
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uEnd()
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{
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this->advance();
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this->upc(0);
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this->nupc(1);
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}
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};
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// A PC with a delay slot.
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template <int InstWidth>
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class DelaySlotPCState : public SimplePCState<InstWidth>
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{
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protected:
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typedef SimplePCState<InstWidth> Base;
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Addr _nnpc;
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public:
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void
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output(std::ostream &os) const override
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{
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ccprintf(os, "(%#x=>%#x=>%#x)", this->pc(), this->npc(), nnpc());
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}
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PCStateBase *
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clone() const override
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{
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return new DelaySlotPCState<InstWidth>(*this);
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}
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void
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update(const PCStateBase &other) override
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{
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Base::update(other);
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auto &pcstate = other.as<DelaySlotPCState<InstWidth>>();
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_nnpc = pcstate._nnpc;
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}
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Addr nnpc() const { return _nnpc; }
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void nnpc(Addr val) { _nnpc = val; }
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void
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set(Addr val)
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{
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Base::set(val);
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nnpc(val + 2 * InstWidth);
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}
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DelaySlotPCState(const DelaySlotPCState &other) :
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Base(other), _nnpc(other._nnpc)
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{}
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DelaySlotPCState &operator=(const DelaySlotPCState &other) = default;
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DelaySlotPCState() {}
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explicit DelaySlotPCState(Addr val) { set(val); }
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bool
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branching() const
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{
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return !(this->nnpc() == this->npc() + InstWidth &&
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(this->npc() == this->pc() + InstWidth ||
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this->npc() == this->pc() + 2 * InstWidth));
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}
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// Advance the PC.
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void
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advance()
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{
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this->_pc = this->_npc;
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this->_npc = this->_nnpc;
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this->_nnpc += InstWidth;
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}
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bool
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equals(const PCStateBase &other) const override
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{
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auto &ps = other.as<DelaySlotPCState<InstWidth>>();
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return Base::equals(other) && ps._nnpc == this->_nnpc;
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}
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void
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serialize(CheckpointOut &cp) const override
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{
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Base::serialize(cp);
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SERIALIZE_SCALAR(_nnpc);
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}
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void
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unserialize(CheckpointIn &cp) override
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{
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Base::unserialize(cp);
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UNSERIALIZE_SCALAR(_nnpc);
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}
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};
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// A PC with a delay slot and a microcode PC.
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template <int InstWidth>
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class DelaySlotUPCState : public DelaySlotPCState<InstWidth>
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{
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protected:
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typedef DelaySlotPCState<InstWidth> Base;
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public:
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void
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output(std::ostream &os) const override
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{
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Base::output(os);
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ccprintf(os, ".(%d=>%d)", this->upc(), this->nupc());
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}
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PCStateBase *
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clone() const override
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{
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return new DelaySlotUPCState<InstWidth>(*this);
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}
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void
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set(Addr val)
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{
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Base::set(val);
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this->upc(0);
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this->nupc(1);
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}
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DelaySlotUPCState(const DelaySlotUPCState &other) : Base(other) {}
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DelaySlotUPCState &operator=(const DelaySlotUPCState &other) = default;
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DelaySlotUPCState() {}
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explicit DelaySlotUPCState(Addr val) { set(val); }
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bool
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branching() const
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{
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return Base::branching() || this->nupc() != this->upc() + 1;
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}
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// Advance the upc within the instruction.
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void
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uAdvance()
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{
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this->_upc = this->_nupc;
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this->_nupc++;
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}
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// End the macroop by resetting the upc and advancing the regular pc.
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void
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uEnd()
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{
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this->advance();
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this->_upc = 0;
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this->_nupc = 1;
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}
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};
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}
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} // namespace gem5
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#endif
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