Mitch Hayenga 96317d466e mem: Add additional tolerance to stride prefetcher ...

Forces the prefetcher to mispredict twice in a row before resetting the
confidence of prefetching.  This helps cases where a load PC strides by a
constant factor, however it may operate on different arrays at times.
Avoids the cost of retraining.  Primarily helps with small iteration loops.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

2014-01-29 23:21:26 -06:00

..

cache

mem: Add additional tolerance to stride prefetcher

2014-01-29 23:21:26 -06:00

protocol

ruby: remove unused label no_vector

2014-01-17 11:02:15 -06:00

ruby

ruby: move all statistics to stats.txt, eliminate ruby.stats

2014-01-10 16:19:47 -06:00

slicc

ruby: move all statistics to stats.txt, eliminate ruby.stats

2014-01-10 16:19:47 -06:00

abstract_mem.cc

mem: Make MemoryAccess flag more verbose

2013-10-17 10:20:45 -05:00

abstract_mem.hh

mem: Avoid explicitly zeroing the memory backing store

2013-05-30 12:53:54 -04:00

AbstractMemory.py

mem: Change AbstractMemory defaults to match the common case

2013-08-19 03:52:33 -04:00

addr_mapper.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

addr_mapper.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

AddrMapper.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

bridge.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

bridge.hh

mem: Tidy up the bridge with const and additional checks

2013-06-27 05:49:49 -04:00

Bridge.py

mem: Tidy up the bridge with const and additional checks

2013-06-27 05:49:49 -04:00

bus.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

bus.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

Bus.py

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

coherent_bus.cc

mem: Make returning snoop responses occupy response layer

2013-05-30 12:54:02 -04:00

coherent_bus.hh

mem: De-virtualise interfaces in the CoherentBus

2013-10-17 10:20:45 -05:00

comm_monitor.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

comm_monitor.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

CommMonitor.py

mem: Add tracing support in the communication monitor

2013-01-07 13:05:37 -05:00

fs_translating_port_proxy.cc

arch: Resurrect the NOISA build target and rename it NULL

2013-09-04 13:22:57 -04:00

fs_translating_port_proxy.hh

arch: Resurrect the NOISA build target and rename it NULL

2013-09-04 13:22:57 -04:00

mem_object.cc

Port: Add protocol-agnostic ports in the port hierarchy

2012-10-15 08:12:35 -04:00

mem_object.hh

Port: Add protocol-agnostic ports in the port hierarchy

2012-10-15 08:12:35 -04:00

MemObject.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

mport.cc

MEM: Separate snoops and normal memory requests/responses

2012-04-14 05:45:07 -04:00

mport.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

noncoherent_bus.cc

mem: Make the buses multi layered

2013-05-30 12:54:01 -04:00

noncoherent_bus.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

packet_access.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

packet_queue.cc

mem: Adding verbose debug output in the memory system

2013-04-22 13:20:33 -04:00

packet_queue.hh

sim: have a curTick per eventq

2012-11-16 10:27:47 -06:00

packet.cc

mem: Add support for a security bit in the memory system

2014-01-24 15:29:30 -06:00

packet.hh

mem: Add support for a security bit in the memory system

2014-01-24 15:29:30 -06:00

page_table.cc

sim: Fix two bugs relating to software caching of PageTable entries.

2013-04-23 09:47:52 -04:00

page_table.hh

sim: Fix two bugs relating to software caching of PageTable entries.

2013-04-23 09:47:52 -04:00

physical.cc

mem: Avoid explicitly zeroing the memory backing store

2013-05-30 12:53:54 -04:00

physical.hh

mem: Merge ranges that are part of the conf table

2013-01-07 13:05:38 -05:00

port_proxy.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

port_proxy.hh

arch: Resurrect the NOISA build target and rename it NULL

2013-09-04 13:22:57 -04:00

port.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

port.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

qport.hh

mem: Add PortID to QueuedMasterPort constructor

2013-10-17 10:20:45 -05:00

request.hh

mem: prefetcher: add options, support for unaligned addresses

2014-01-29 23:21:25 -06:00

SConscript

mem: Use the same timing calculation for DRAM read and write

2013-11-01 11:56:19 -04:00

se_translating_port_proxy.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

se_translating_port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

simple_dram.cc

mem: Fixes a bug in simple_dram write merging

2014-01-28 18:00:49 -06:00

simple_dram.hh

mem: Fixes for DRAM stats accounting

2013-11-01 11:56:31 -04:00

simple_mem.cc

mem: Fix scheduling bug in SimpleMemory

2013-09-18 08:46:33 -04:00

simple_mem.hh

mem: Add an internal packet queue in SimpleMemory

2013-08-19 03:52:25 -04:00

SimpleDRAM.py

mem: Fix the LPDDR3 page size

2013-11-01 11:56:30 -04:00

SimpleMemory.py

mem: Add an internal packet queue in SimpleMemory

2013-08-19 03:52:25 -04:00

tport.cc

mem: Replace check with panic where inhibited should not happen

2013-04-22 13:20:33 -04:00

tport.hh

Port: Hide the queue implementation in SimpleTimingPort

2012-07-09 12:35:42 -04:00