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c1513c69cad2c26c6dcb66416e152952ceb0597e
gem5/src/arch/arm
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Curtis Dunham c1513c69ca arm: extend MiscReg metadata structures 
Implement proper handling of RES0/RES1 and RAZ/RAO bitfields.

Change-Id: I344c32c3fb1d142acfb0521ba3590ddd2b1f5360
Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6802
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29 22:31:20 +00:00
..
freebsd
arm: Remove unused DumpStatsPCEventF class in FreeBSD system
2017-05-12 09:21:41 +00:00
insts
arch-arm: Fixed WFE/WFI trapping behaviour
2017-12-21 13:25:24 +00:00
isa
arch-arm: Fixed WFE/WFI trapping behaviour
2017-12-21 13:25:24 +00:00
kvm
kvm: arm: Get rid of functions which just wrap the subclasses version.
2017-09-20 17:55:09 +00:00
linux
arm,sim: fix context switch stats dumps for ARM64/Linux
2017-06-22 13:32:04 +00:00
ArmInterrupts.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
ArmISA.py
cpu: Added interface for vector reg file
2017-07-05 14:43:49 +00:00
ArmNativeTrace.py
cpu: Put all CPU instruction tracers in a single file
2015-01-25 07:22:17 -05:00
ArmPMU.py
arch-arm: ArmPMU refactor
2017-11-21 17:09:18 +00:00
ArmSystem.py
arm: DT autogeneration - Generate memory node
2018-01-29 22:22:06 +00:00
ArmTLB.py
arm, power: Make the python TLB simobjects inherit from BaseTLB.
2018-01-11 09:34:23 +00:00
ccregs.hh
arm: use condition code registers for ARM ISA
2014-04-29 16:05:02 -05:00
decoder.cc
isa: Add parameter to pick different decoder inside ISA
2015-10-09 14:50:54 -05:00
decoder.hh
isa: Add parameter to pick different decoder inside ISA
2015-10-09 14:50:54 -05:00
faults.cc
arch-arm: Hyp routed undef fault need to change its syndrome
2017-12-21 13:25:24 +00:00
faults.hh
arch-arm: Hyp routed undef fault need to change its syndrome
2017-12-21 13:25:24 +00:00
interrupts.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
interrupts.hh
arm: Fix secure state checking in various places
2016-08-02 10:38:02 +01:00
intregs.hh
arm: ISA X31 destination register fix
2014-09-03 07:42:43 -04:00
isa_device.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
isa_device.hh
misc: Remove redundant compiler-specific defines
2015-10-12 04:07:59 -04:00
isa_traits.hh
alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.
2018-01-10 12:19:54 +00:00
isa.cc
arm: extend MiscReg metadata structures
2018-01-29 22:31:20 +00:00
isa.hh
arm: extend MiscReg metadata structures
2018-01-29 22:31:20 +00:00
kernel_stats.hh
stats: Get rid of some kernel stats related cruft.
2017-09-11 04:58:38 +00:00
locked_mem.hh
mem: Signal the local monitor when clearing the global monitor
2017-10-13 08:41:08 +00:00
microcode_rom.hh
arm: include missing file for arm
2009-04-21 15:40:26 -07:00
miscregs.cc
arm: Change access permission in TPIDRURO and TPIDRURW
2017-12-08 18:23:09 +00:00
miscregs.hh
arm: Don't panic when checking coprocessor read/write permissions
2017-04-03 16:39:47 +00:00
mmapped_ipr.hh
arch: Add support for m5ops using mmapped IPRs
2013-09-30 12:20:43 +02:00
nativetrace.cc
cpu: Added interface for vector reg file
2017-07-05 14:43:49 +00:00
nativetrace.hh
ARM: Add vfpv3 support to native trace.
2011-05-04 20:38:26 -05:00
pagetable.hh
arm: Mark uninitialized new TLB entries as not valid
2016-06-20 15:51:31 +01:00
pmu.cc
arch-arm: ArmPMU refactor
2017-11-21 17:09:18 +00:00
pmu.hh
arch-arm: ArmPMU refactor
2017-11-21 17:09:18 +00:00
process.cc
arch, mem, sim: Consolidate and rename the SE mode page table classes.
2018-01-19 20:20:57 +00:00
process.hh
arch,mem: Move page table construction into the arch classes.
2018-01-11 06:29:58 +00:00
pseudo_inst.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
registers.hh
cpu: Added interface for vector reg file
2017-07-05 14:43:49 +00:00
remote_gdb.cc
arch, mem: Make the page table lookup function return a pointer.
2018-01-20 08:06:56 +00:00
remote_gdb.hh
sim, arch, base: Refactor the base remote GDB class.
2018-01-20 07:28:42 +00:00
SConscript
scons: Stop generating inc.d in the isa parser.
2017-10-17 18:57:50 +00:00
SConsopts
arm: add ARM support to M5
2009-04-05 18:53:15 -07:00
stacktrace.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
stacktrace.hh
arch: Use const StaticInstPtr references where possible
2014-09-27 09:08:36 -04:00
stage2_lookup.cc
style: change C/C++ source permissions to noexec
2018-01-10 16:49:23 +00:00
stage2_lookup.hh
style: change C/C++ source permissions to noexec
2018-01-10 16:49:23 +00:00
stage2_mmu.cc
style: change C/C++ source permissions to noexec
2018-01-10 16:49:23 +00:00
stage2_mmu.hh
style: change C/C++ source permissions to noexec
2018-01-10 16:49:23 +00:00
system.cc
arch-arm: Add haveEL pseudocode function
2017-11-28 12:00:30 +00:00
system.hh
arch-arm: Add haveEL pseudocode function
2017-11-28 12:00:30 +00:00
table_walker.cc
arch,cpu: "virtualize" the TLB interface.
2017-12-22 23:16:03 +00:00
table_walker.hh
arm: Replace EventWrapper use with EventFunctionWrapper
2017-06-20 18:03:21 +00:00
tlb.cc
arch,cpu: "virtualize" the TLB interface.
2017-12-22 23:16:03 +00:00
tlb.hh
arm: Make translateFunctional override the base implementation.
2018-01-09 03:01:41 +00:00
types.hh
arm, base: Generalize and move the BitUnion hash struct.
2018-01-20 07:30:26 +00:00
utility.cc
arch,cpu: "virtualize" the TLB interface.
2017-12-22 23:16:03 +00:00
utility.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
vtophys.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
vtophys.hh
gcc: Clean-up of non-C++0x compliant code, first steps
2012-03-19 06:36:09 -04:00