Kevin Lim c1046488e0 Move TLB faults into the normal Fault code. The TLB no longer fills in IPRs through its own fault() method; this is handled by the fault's invoke() methods. ...

arch/alpha/faults.cc:
    Move TLB fault code into the normal fault invoke() method.
arch/alpha/faults.hh:
    Move DTB/ITB fault handling code into their own class with a specific invoke() method.  Have DTB/ITB faults derive from these classes.

    Unfortunately the DtbAlignmentFault is somewhat odd; it's a normal alignment fault, but it must also set some specific IPRs.
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
    Setting IPRs is now handled through the fault itself.

--HG--
extra : convert_revision : 5cb92ce2186ff79f632bfcbc9ba62a8a04400eae

2006-03-28 18:01:01 -05:00

..

alpha

Move TLB faults into the normal Fault code. The TLB no longer fills in IPRs through its own fault() method; this is handled by the fault's invoke() methods.

2006-03-28 18:01:01 -05:00

mips

support for unaligned memory access

2006-03-19 13:40:03 -05:00

sparc

Moving towards compilation.

2006-03-28 15:13:57 -05:00

isa_parser.py

Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.

2006-03-14 15:55:00 -05:00

isa_specific.hh

Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu

2006-03-14 18:28:51 -05:00

SConscript

Moved registerfile.hh to regfile.hh

2006-03-14 16:05:44 -05:00