support for unaligned memory access

arch/mips/isa/base.isa:
    disassembly fixes
arch/mips/isa/decoder.isa:
    support for unaligned loads/stores
arch/mips/isa_traits.hh:
    edit Syscall Reg values
arch/mips/linux_process.cc:
    call writevFunc on writev syscall

--HG--
extra : convert_revision : 4aea6d069bd7ba0e83b23d2d85c50d68532f0454

arch/mips/isa/base.isa

@@ -67,12 +67,11 @@ output decoder {{
         ccprintf(ss, "%-10s ", mnemonic);
 
         if(_numDestRegs > 0){
-            if(_numSrcRegs > 0)
-                ss << ",";
             printReg(ss, _destRegIdx[0]);
         }
 
         if(_numSrcRegs > 0) {
+            ss << ",";
             printReg(ss, _srcRegIdx[0]);
         }
 
@@ -82,8 +81,8 @@ output decoder {{
         }
 
 
-        if(mnemonic == "sll"){
-            ccprintf(ss," %d",SA);
+        if(mnemonic == "sll" || mnemonic == "sra"){
+            ccprintf(ss,", %d",SA);
         }
 
         return ss.str();

arch/mips/isa/decoder.isa

@@ -865,11 +865,11 @@ decode OPCODE_HI default Unknown::unknown() {
         format LoadMemory {
             0x0: lb({{ Rt.sw = Mem.sb; }});
             0x1: lh({{ Rt.sw = Mem.sh; }});
-            0x2: lwl({{ Rt.sw = Mem.sw; }});//, WordAlign);
+            0x2: lwl({{ uint32_t temp = Mem.uw<31:16> << 16; Rt.uw &= 0x00FF; Rt.uw |= temp;}}, {{ EA = (Rs + disp) & ~3; }});
             0x3: lw({{ Rt.sw = Mem.sw; }});
             0x4: lbu({{ Rt.uw = Mem.ub; }});
             0x5: lhu({{ Rt.uw = Mem.uh; }});
-            0x6: lwr({{ Rt.uw = Mem.uw; }});//, WordAlign);
+            0x6: lwr({{ uint32_t temp = 0x00FF & Mem.uw<15:0>; Rt.uw &= 0xFF00; Rt.uw |= temp; }}, {{ EA = (Rs + disp) & ~3; }});
         }
 
         0x7: FailUnimpl::reserved();
@@ -879,9 +879,9 @@ decode OPCODE_HI default Unknown::unknown() {
         format StoreMemory {
             0x0: sb({{ Mem.ub = Rt<7:0>; }});
             0x1: sh({{ Mem.uh = Rt<15:0>; }});
-            0x2: swl({{ Mem.uw = Rt<31:0>; }});//,WordAlign);
+            0x2: swl({{ Mem.uh = Rt<31:16>; }}, {{ EA = (Rs + disp) & ~3; }});
             0x3: sw({{ Mem.uw = Rt<31:0>; }});
-            0x6: swr({{ Mem.uw = Rt<31:0>; }});//,WordAlign);
+            0x6: swr({{ Mem.uh = Rt<15:0>; }},{{ EA = ((Rs + disp) & ~3) + 4;}});
         }
 
         format WarnUnimpl {

arch/mips/isa_traits.hh

@@ -136,8 +136,8 @@ namespace MipsISA
     const int ReturnAddressReg = 31;
 
     const int SyscallNumReg = ReturnValueReg1;
-    const int SyscallPseudoReturnReg = ArgumentReg3;
-    const int SyscallSuccessReg = 19;
+    const int SyscallPseudoReturnReg = ReturnValueReg1;
+    const int SyscallSuccessReg = ReturnValueReg1;
 
     const int LogVMPageSize = 13;	// 8K bytes
     const int VMPageSize = (1 << LogVMPageSize);

arch/mips/linux_process.cc

@@ -237,7 +237,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
     /* 119 */ SyscallDesc("sigreturn", unimplementedFunc),
     /* 120 */ SyscallDesc("clone", unimplementedFunc),
     /* 121 */ SyscallDesc("setdomainname", unimplementedFunc),
-    /* 122 */ SyscallDesc("uname", unameFunc),/*,writevFunc<Linux>*/
+    /* 122 */ SyscallDesc("uname", unameFunc),
     /* 123 */ SyscallDesc("modify_ldt", unimplementedFunc),
     /* 124 */ SyscallDesc("adjtimex", unimplementedFunc),
     /* 125 */ SyscallDesc("mprotect", unimplementedFunc),
@@ -261,7 +261,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
     /* 143 */ SyscallDesc("flock", unimplementedFunc),
     /* 144 */ SyscallDesc("msync", unimplementedFunc),/*getrlimitFunc<Linux>*/
     /* 145 */ SyscallDesc("readv", unimplementedFunc),
-    /* 146 */ SyscallDesc("writev", unimplementedFunc/*writeFunc*/),
+    /* 146 */ SyscallDesc("writev", writevFunc<Linux>),
     /* 147 */ SyscallDesc("cacheflush", unimplementedFunc),
     /* 148 */ SyscallDesc("cachectl", unimplementedFunc),
     /* 149 */ SyscallDesc("sysmips", unimplementedFunc),