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bebed8544aa9eac75288698b5d3add1187b6f726
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Matthew Poremba bebed8544a dev-amdgpu: Hotfix variable initialization 
These non-initialized variables were causing the trace reader not to
record all lines.

Change-Id: I88764493d8124c072bc90ff9c08aa26421467f7b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53063
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-07 18:16:10 +00:00
..
amdgpu
dev-amdgpu: Hotfix variable initialization
2021-12-07 18:16:10 +00:00
arm
misc: Stop including arch/pcstate.hh.
2021-11-30 23:30:06 +00:00
hsa
dev,gpu-compute: Use a TranslationGen in DmaVirtDevice.
2021-10-22 21:43:02 +00:00
i2c
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mips
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
net
misc: Use python 3's argumentless super().
2021-11-09 13:04:44 +00:00
pci
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
ps2
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
riscv
dev: Separate generateDeviceTree into a RiscvUart8250 SimObject.
2021-10-28 20:27:16 +00:00
serial
dev: Separate generateDeviceTree into a RiscvUart8250 SimObject.
2021-10-28 20:27:16 +00:00
sparc
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
storage
misc: Replace GEM5_FALLTHROUGH with [[fallthrough]].
2021-07-24 21:57:04 +00:00
virtio
cpu-kvm,arch-x86,arch-arm,dev: Pair operator new with operator delete.
2021-11-04 04:39:24 +00:00
x86
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
baddev.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
baddev.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
BadDevice.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
Device.py
dev,dev-hsa,gpu-compute: Refactor dmaVirt calls
2021-07-09 22:40:18 +00:00
dma_device.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dma_device.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dma_virt_device.cc
dev,gpu-compute: Use a TranslationGen in DmaVirtDevice.
2021-10-22 21:43:02 +00:00
dma_virt_device.hh
dev,gpu-compute: Use a TranslationGen in DmaVirtDevice.
2021-10-22 21:43:02 +00:00
intel_8254_timer.cc
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
intel_8254_timer.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
intpin.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
intpin.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
IntPin.py
misc: Use python 3's argumentless super().
2021-11-09 13:04:44 +00:00
io_device.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
io_device.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa_fake.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa_fake.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mc146818.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mc146818.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pixelpump.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pixelpump.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
platform.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
platform.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
Platform.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
reg_bank.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
reg_bank.test.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
rtcreg.h
dev: Delete the authors list from files in src/dev.
2020-02-18 03:34:01 +00:00
SConscript
dev,dev-hsa,gpu-compute: Refactor dmaVirt calls
2021-07-09 22:40:18 +00:00