Matt Sinclair bd7eadb467 x86,misc: add additional info on faulting X86 instruction, fetched PC ...

Print faulting instruction for unmapped address panic in faults.cc
and print extra info about corresponding fetched PC in base.cc.

Change-Id: Id9e15d3e88df2ad6b809fb3cf9f6ae97e9e97e0f
Reviewed-on: https://gem5-review.googlesource.com/6461
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

2017-12-08 04:05:58 +00:00

..

alpha

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

arm

arm: Add support for the dc {civac, cvac, cvau, ivac} instr

2017-12-05 11:47:01 +00:00

generic

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

hsail

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

mips

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

null

scons: Stop generating inc.d in the isa parser.

2017-10-17 18:57:50 +00:00

power

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

riscv

arch-riscv: Move compressed ops out of ISA

2017-12-07 03:14:09 +00:00

sparc

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

x86

x86,misc: add additional info on faulting X86 instruction, fetched PC

2017-12-08 04:05:58 +00:00

isa_parser.py

alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.

2017-11-02 09:43:35 +00:00

micro_asm_test.py

Add a second section to make sure the ROM is extended properly.

2007-05-31 22:21:21 +00:00

micro_asm.py

scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access

2009-09-22 15:24:16 -07:00

SConscript

scons: Move Transform and termcap functionality into their own files.

2017-11-10 13:17:29 +00:00