Alex Richardson bd687d48eb arch-riscv: Add an ostream operator for PrivilegeMode ...

This makes it easier to use the current privilege mode in error messages.

Change-Id: I425d45d3957a70d8afb6cbde18955fae1461c960
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55403
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2022-01-13 10:44:48 +00:00

..

arch

arch-riscv: Add an ostream operator for PrivilegeMode

2022-01-13 10:44:48 +00:00

base

base: Add missing ']' in version ID

2022-01-07 19:06:44 +00:00

cpu

cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.

2022-01-12 15:59:27 +00:00

dev

dev-arm: Mask el2_watchdog in VExpressFastmodel platform

2022-01-12 08:07:43 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

misc: Remove AMD license addition

2021-12-11 04:00:56 +00:00

kern

sim-se: Add additional TGT_AT_* constants for Linux.

2021-11-24 22:48:17 +00:00

learning_gem5

scons: Add sim_object and enums arguments to SimObject().

2021-12-08 08:01:23 +00:00

mem

misc: Generate StateMachine debug includes in deterministic order

2022-01-05 10:15:55 +00:00

proto

sim,misc: Move protobuf housekeeping out of gem5Main.

2021-12-08 08:01:23 +00:00

python

python,util: Pull enum hh|cc generation out of the MetaEnum class.

2022-01-13 05:21:41 +00:00

sim

scons,sim: Eliminate the generated cxx_config/init.cc file.

2022-01-13 05:21:41 +00:00

sst

scons: Add sim_object and enums arguments to SimObject().

2021-12-08 08:01:23 +00:00

systemc

misc: Merge branch 'release-staging-v21-2' into develop

2021-12-16 23:07:43 -08:00

Doxyfile

misc: Revert v21.2 specific commits for develop

2021-12-28 21:30:21 +00:00

SConscript

scons,sim: Eliminate the generated cxx_config/init.cc file.

2022-01-13 05:21:41 +00:00