afee6296b5
The upgraders in util/cpt_upgraders have been able to check the root.isa element of checkpoints to determine what "the" ISA is for a simulation, as a quick way to bail out of that particular updater applies only to specific ISAs. We are moving away from the idea that there is a single ISA, and so this mechanism will no longer work. Fortunately, these cpt_upgraders are only relevant for old checkpoints. If a checkpoint doesn't have a root.isa element inside it at all, we know (as of this writing) that it is newer than all of these upgraders and hence they do not apply. Any new upgraders will have to be written to not rely on the root.isa field which will be removed. If that sort of field is still needed, it can be added somewhere else in the hierarchy, perhaps at the system level, or as part of the actual ISA object. The simplest way to implement this new behavior is to add a fallback option when an upgrader looks for root.isa, specifically ''. If the root.isa element does not exist, the script will get '' back, and this will not match whatever ISA it's trying to check against. The one even remotely more complicated script is isa-is-simobject.py which has several behaviors for different ISAs. In that case, we just explicitly check for '' and return early if that's what we found. Jira Issue: https://gem5.atlassian.net/browse/GEM5-1056 Change-Id: Ie78deccb2bac51f38224e62a28dd733cefd63ed7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48883 Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
315 lines
13 KiB
Python
315 lines
13 KiB
Python
# Add all ARMv8 state
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def upgrader(cpt):
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if cpt.get('root', 'isa', fallback='') != 'arm':
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return
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import re
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print("Warning: The size of the FP register file has changed. "
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"To get similar results you need to adjust the number of "
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"physical registers in the CPU you're restoring into by "
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"NNNN.")
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# Find the CPU context's and upgrade their registers
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for sec in cpt.sections():
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re_xc_match = re.match('^.*?sys.*?\.cpu(\d+)*\.xc\.*', sec)
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if not re_xc_match:
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continue
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# Update floating point regs
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fpr = cpt.get(sec, 'floatRegs.i').split()
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# v8 has 128 normal fp and 32 special fp regs compared
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# to v7's 64 normal fp and 8 special fp regs.
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# Insert the extra normal fp registers at end of v7 normal fp regs
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for x in range(64):
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fpr.insert(64, "0")
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# Append the extra special registers
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for x in range(24):
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fpr.append("0")
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cpt.set(sec, 'floatRegs.i', ' '.join(str(x) for x in fpr))
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ir = cpt.get(sec, 'intRegs').split()
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# Add in v8 int reg state
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# Splice in R13_HYP
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ir.insert(20, "0")
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# Splice in INTREG_DUMMY and SP0 - SP3
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ir.extend(["0", "0", "0", "0", "0"])
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cpt.set(sec, 'intRegs', ' '.join(str(x) for x in ir))
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# Update the cpu interrupt field
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for sec in cpt.sections():
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re_int_match = re.match("^.*?sys.*?\.cpu(\d+)*$", sec)
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if not re_int_match:
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continue
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irqs = cpt.get(sec, "interrupts").split()
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irqs.append("false")
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irqs.append("false")
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cpt.set(sec, "interrupts", ' '.join(str(x) for x in irqs))
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# Update the per cpu interrupt structure
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for sec in cpt.sections():
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re_int_match = re.match("^.*?sys.*?\.cpu(\d+)*\.interrupts$", sec)
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if not re_int_match:
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continue
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irqs = cpt.get(sec, "interrupts").split()
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irqs.append("false")
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irqs.append("false")
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cpt.set(sec, "interrupts", ' '.join(str(x) for x in irqs))
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# Update the misc regs and add in new isa specific fields
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for sec in cpt.sections():
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re_isa_match = re.match("^.*?sys.*?\.cpu(\d+)*\.isa$", sec)
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if not re_isa_match:
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continue
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cpt.set(sec, 'haveSecurity', 'false')
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cpt.set(sec, 'haveLPAE', 'false')
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cpt.set(sec, 'haveVirtualization', 'false')
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cpt.set(sec, 'haveLargeAsid64', 'false')
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cpt.set(sec, 'physAddrRange64', '40')
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# splice in the new misc registers, ~200 -> 605 registers,
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# ordering does not remain consistent
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mr_old = cpt.get(sec, 'miscRegs').split()
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mr_new = [ '0' for x in range(605) ]
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# map old v7 miscRegs to new v8 miscRegs
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mr_new[0] = mr_old[0] # CPSR
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mr_new[16] = mr_old[1] # CPSR_Q
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mr_new[1] = mr_old[2] # SPSR
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mr_new[2] = mr_old[3] # SPSR_FIQ
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mr_new[3] = mr_old[4] # SPSR_IRQ
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mr_new[4] = mr_old[5] # SPSR_SVC
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mr_new[5] = mr_old[6] # SPSR_MON
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mr_new[8] = mr_old[7] # SPSR_UND
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mr_new[6] = mr_old[8] # SPSR_ABT
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mr_new[432] = mr_old[9] # FPSR
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mr_new[10] = mr_old[10] # FPSID
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mr_new[11] = mr_old[11] # FPSCR
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mr_new[18] = mr_old[12] # FPSCR_QC
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mr_new[17] = mr_old[13] # FPSCR_EXC
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mr_new[14] = mr_old[14] # FPEXC
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mr_new[13] = mr_old[15] # MVFR0
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mr_new[12] = mr_old[16] # MVFR1
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mr_new[28] = mr_old[17] # SCTLR_RST,
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mr_new[29] = mr_old[18] # SEV_MAILBOX,
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mr_new[30] = mr_old[19] # DBGDIDR
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mr_new[31] = mr_old[20] # DBGDSCR_INT,
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mr_new[33] = mr_old[21] # DBGDTRRX_INT,
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mr_new[34] = mr_old[22] # DBGTRTX_INT,
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mr_new[35] = mr_old[23] # DBGWFAR,
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mr_new[36] = mr_old[24] # DBGVCR,
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#mr_new[] = mr_old[25] # DBGECR -> UNUSED,
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#mr_new[] = mr_old[26] # DBGDSCCR -> UNUSED,
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#mr_new[] = mr_old[27] # DBGSMCR -> UNUSED,
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mr_new[37] = mr_old[28] # DBGDTRRX_EXT,
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mr_new[38] = mr_old[29] # DBGDSCR_EXT,
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mr_new[39] = mr_old[30] # DBGDTRTX_EXT,
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#mr_new[] = mr_old[31] # DBGDRCR -> UNUSED,
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mr_new[41] = mr_old[32] # DBGBVR,
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mr_new[47] = mr_old[33] # DBGBCR,
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#mr_new[] = mr_old[34] # DBGBVR_M -> UNUSED,
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#mr_new[] = mr_old[35] # DBGBCR_M -> UNUSED,
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mr_new[61] = mr_old[36] # DBGDRAR,
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#mr_new[] = mr_old[37] # DBGBXVR_M -> UNUSED,
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mr_new[64] = mr_old[38] # DBGOSLAR,
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#mr_new[] = mr_old[39] # DBGOSSRR -> UNUSED,
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mr_new[66] = mr_old[40] # DBGOSDLR,
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mr_new[67] = mr_old[41] # DBGPRCR,
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#mr_new[] = mr_old[42] # DBGPRSR -> UNUSED,
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mr_new[68] = mr_old[43] # DBGDSAR,
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#mr_new[] = mr_old[44] # DBGITCTRL -> UNUSED,
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mr_new[69] = mr_old[45] # DBGCLAIMSET,
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mr_new[70] = mr_old[46] # DBGCLAIMCLR,
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mr_new[71] = mr_old[47] # DBGAUTHSTATUS,
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mr_new[72] = mr_old[48] # DBGDEVID2,
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mr_new[73] = mr_old[49] # DBGDEVID1,
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mr_new[74] = mr_old[50] # DBGDEVID,
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mr_new[77] = mr_old[51] # TEEHBR,
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mr_new[109] = mr_old[52] # v7 SCTLR -> aarc32 SCTLR_NS
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mr_new[189] = mr_old[53] # DCCISW,
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mr_new[188] = mr_old[54] # DCCIMVAC,
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mr_new[183] = mr_old[55] # DCCMVAC,
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mr_new[271] = mr_old[56] # v7 CONTEXTIDR -> aarch32 CONTEXTIDR_NS,
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mr_new[274] = mr_old[57] # v7 TPIDRURW -> aarch32 TPIDRURW_NS,
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mr_new[277] = mr_old[58] # v7 TPIDRURO -> aarch32 TPIDRURO_NS,
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mr_new[280] = mr_old[59] # v7 TPIDRPRW -> aarch32 TPIDRPRW_NS,
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mr_new[170] = mr_old[60] # CP15ISB,
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mr_new[185] = mr_old[61] # CP15DSB,
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mr_new[186] = mr_old[62] # CP15DMB,
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mr_new[114] = mr_old[63] # CPACR,
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mr_new[101] = mr_old[64] # CLIDR,
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mr_new[100] = mr_old[65] # CCSIDR,
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mr_new[104] = mr_old[66] # v7 CSSELR -> aarch32 CSSELR_NS,
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mr_new[163] = mr_old[67] # ICIALLUIS,
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mr_new[168] = mr_old[68] # ICIALLU,
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mr_new[169] = mr_old[69] # ICIMVAU,
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mr_new[172] = mr_old[70] # BPIMVA,
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mr_new[164] = mr_old[71] # BPIALLIS,
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mr_new[171] = mr_old[72] # BPIALL,
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mr_new[80] = mr_old[73] # MIDR,
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mr_new[126] = mr_old[74] # v7 TTBR0 -> aarch32 TTBR0_NS,
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mr_new[129] = mr_old[75] # v7 TTBR1 -> aarch32 TTBR1_NS,
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mr_new[83] = mr_old[76] # TLBTR,
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mr_new[137] = mr_old[77] # v7 DACR -> aarch32 DACR_NS,
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mr_new[192] = mr_old[78] # TLBIALLIS,
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mr_new[193] = mr_old[79] # TLBIMVAIS,
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mr_new[194] = mr_old[80] # TLBIASIDIS,
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mr_new[195] = mr_old[81] # TLBIMVAAIS,
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mr_new[198] = mr_old[82] # ITLBIALL,
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mr_new[199] = mr_old[83] # ITLBIMVA,
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mr_new[200] = mr_old[84] # ITLBIASID,
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mr_new[201] = mr_old[85] # DTLBIALL,
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mr_new[202] = mr_old[86] # DTLBIMVA,
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mr_new[203] = mr_old[87] # DTLBIASID,
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mr_new[204] = mr_old[88] # TLBIALL,
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mr_new[205] = mr_old[89] # TLBIMVA,
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mr_new[206] = mr_old[90] # TLBIASID,
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mr_new[207] = mr_old[91] # TLBIMVAA,
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mr_new[140] = mr_old[92] # v7 DFSR -> aarch32 DFSR_NS,
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mr_new[143] = mr_old[93] # v7 IFSR -> aarch32 IFSR_NS,
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mr_new[155] = mr_old[94] # v7 DFAR -> aarch32 DFAR_NS,
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mr_new[158] = mr_old[95] # v7 IFAR -> aarch32 IFAR_NS,
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mr_new[84] = mr_old[96] # MPIDR,
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mr_new[241] = mr_old[97] # v7 PRRR -> aarch32 PRRR_NS,
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mr_new[247] = mr_old[98] # v7 NMRR -> aarch32 NMRR_NS,
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mr_new[131] = mr_old[99] # TTBCR,
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mr_new[86] = mr_old[100] # ID_PFR0,
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mr_new[81] = mr_old[101] # CTR,
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mr_new[115] = mr_old[102] # SCR,
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# Set the non-secure bit
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scr = int(mr_new[115])
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scr = scr | 0x1
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mr_new[115] = str(scr)
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###
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mr_new[116] = mr_old[103] # SDER,
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mr_new[165] = mr_old[104] # PAR,
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mr_new[175] = mr_old[105] # V2PCWPR -> ATS1CPR,
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mr_new[176] = mr_old[106] # V2PCWPW -> ATS1CPW,
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mr_new[177] = mr_old[107] # V2PCWUR -> ATS1CUR,
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mr_new[178] = mr_old[108] # V2PCWUW -> ATS1CUW,
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mr_new[179] = mr_old[109] # V2POWPR -> ATS12NSOPR,
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mr_new[180] = mr_old[110] # V2POWPW -> ATS12NSOPW,
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mr_new[181] = mr_old[111] # V2POWUR -> ATS12NSOUR,
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mr_new[182] = mr_old[112] # V2POWUW -> ATS12NWOUW,
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mr_new[90] = mr_old[113] # ID_MMFR0,
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mr_new[92] = mr_old[114] # ID_MMFR2,
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mr_new[93] = mr_old[115] # ID_MMFR3,
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mr_new[112] = mr_old[116] # v7 ACTLR -> aarch32 ACTLR_NS
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mr_new[222] = mr_old[117] # PMCR,
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mr_new[230] = mr_old[118] # PMCCNTR,
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mr_new[223] = mr_old[119] # PMCNTENSET,
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mr_new[224] = mr_old[120] # PMCNTENCLR,
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mr_new[225] = mr_old[121] # PMOVSR,
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mr_new[226] = mr_old[122] # PMSWINC,
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mr_new[227] = mr_old[123] # PMSELR,
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mr_new[228] = mr_old[124] # PMCEID0,
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mr_new[229] = mr_old[125] # PMCEID1,
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mr_new[231] = mr_old[126] # PMXEVTYPER,
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mr_new[233] = mr_old[127] # PMXEVCNTR,
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mr_new[234] = mr_old[128] # PMUSERENR,
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mr_new[235] = mr_old[129] # PMINTENSET,
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mr_new[236] = mr_old[130] # PMINTENCLR,
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mr_new[94] = mr_old[131] # ID_ISAR0,
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mr_new[95] = mr_old[132] # ID_ISAR1,
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mr_new[96] = mr_old[133] # ID_ISAR2,
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mr_new[97] = mr_old[134] # ID_ISAR3,
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mr_new[98] = mr_old[135] # ID_ISAR4,
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mr_new[99] = mr_old[136] # ID_ISAR5,
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mr_new[20] = mr_old[137] # LOCKFLAG,
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mr_new[19] = mr_old[138] # LOCKADDR,
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mr_new[87] = mr_old[139] # ID_PFR1,
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# Set up the processor features register
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pfr = int(mr_new[87])
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pfr = pfr | 0x1011
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mr_new[87] = str(pfr)
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###
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mr_new[238] = mr_old[140] # L2CTLR,
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mr_new[82] = mr_old[141] # TCMTR
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mr_new[88] = mr_old[142] # ID_DFR0,
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mr_new[89] = mr_old[143] # ID_AFR0,
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mr_new[91] = mr_old[144] # ID_MMFR1,
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mr_new[102] = mr_old[145] # AIDR,
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mr_new[146] = mr_old[146] # v7 ADFSR -> aarch32 ADFSR_NS,
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mr_new[148] = mr_old[147] # AIFSR,
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mr_new[173] = mr_old[148] # DCIMVAC,
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mr_new[174] = mr_old[149] # DCISW,
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mr_new[184] = mr_old[150] # MCCSW -> DCCSW,
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mr_new[187] = mr_old[151] # DCCMVAU,
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mr_new[117] = mr_old[152] # NSACR,
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mr_new[262] = mr_old[153] # VBAR,
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mr_new[265] = mr_old[154] # MVBAR,
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mr_new[267] = mr_old[155] # ISR,
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mr_new[269] = mr_old[156] # FCEIDR -> FCSEIDR,
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#mr_new[] = mr_old[157] # L2LATENCY -> UNUSED,
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#mr_new[] = mr_old[158] # CRN15 -> UNUSED,
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mr_new[599] = mr_old[159] # NOP
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mr_new[600] = mr_old[160] # RAZ,
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# Set the new miscRegs structure
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cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr_new))
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cpu_prefix = {}
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# Add in state for ITB/DTB
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for sec in cpt.sections():
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re_tlb_match = re.match('(^.*?sys.*?\.cpu(\d+)*)\.(dtb|itb)$', sec)
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if not re_tlb_match:
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continue
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cpu_prefix[re_tlb_match.group(1)] = True # Save off prefix to add
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# Set the non-secure bit (bit 9) to 1 for attributes
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attr = int(cpt.get(sec, '_attr'))
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attr = attr | 0x200
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cpt.set(sec, '_attr', str(attr))
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cpt.set(sec, 'haveLPAE', 'false')
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cpt.set(sec, 'directToStage2', 'false')
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cpt.set(sec, 'stage2Req', 'false')
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cpt.set(sec, 'bootUncacheability', 'true')
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# Add in extra state for the new TLB Entries
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for sec in cpt.sections():
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re_tlbentry_match = re.match('(^.*?sys.*?\.cpu(\d+)*)\.(dtb|itb).TlbEntry\d+$', sec)
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if not re_tlbentry_match:
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continue
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# Add in the new entries
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cpt.set(sec, 'longDescFormat', 'false')
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cpt.set(sec, 'vmid', '0')
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cpt.set(sec, 'isHyp', 'false')
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valid = cpt.get(sec, 'valid')
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if valid == 'true':
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cpt.set(sec, 'ns', 'true')
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cpt.set(sec, 'nstid', 'true')
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cpt.set(sec, 'pxn', 'true')
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cpt.set(sec, 'hap', '3')
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# All v7 code used 2 level page tables
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cpt.set(sec, 'lookupLevel', '2')
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attr = int(cpt.get(sec, 'attributes'))
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# set the non-secure bit (bit 9) to 1
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# as no previous v7 code used secure code
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attr = attr | 0x200
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cpt.set(sec, 'attributes', str(attr))
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else:
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cpt.set(sec, 'ns', 'false')
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cpt.set(sec, 'nstid', 'false')
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cpt.set(sec, 'pxn', 'false')
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cpt.set(sec, 'hap', '0')
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cpt.set(sec, 'lookupLevel', '0')
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cpt.set(sec, 'outerShareable', 'false')
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# Add d/istage2_mmu and d/istage2_mmu.stage2_tlb
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for key in cpu_prefix:
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for suffix in ['.istage2_mmu', '.dstage2_mmu']:
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new_sec = key + suffix
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cpt.add_section(new_sec)
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new_sec = key + suffix + ".stage2_tlb"
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cpt.add_section(new_sec)
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# Fill in tlb info with some defaults
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cpt.set(new_sec, '_attr', '0')
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cpt.set(new_sec, 'haveLPAE', 'false')
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cpt.set(new_sec, 'directToStage2', 'false')
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cpt.set(new_sec, 'stage2Req', 'false')
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cpt.set(new_sec, 'bootUncacheability', 'false')
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cpt.set(new_sec, 'num_entries', '0')
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legacy_version = 9
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