34826f1892
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: Id7aafc082c7e4cfc977e807141e63a3feb5a6348 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52863 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
64 lines
2.6 KiB
Python
64 lines
2.6 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import m5
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from m5.objects import *
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nb_cores = 4
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cpus = [ DerivO3CPU(cpu_id=i) for i in range(nb_cores) ]
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import ruby_config
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ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
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# system simulated
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system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
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mem_mode = "timing",
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clk_domain = SrcClockDomain(clock = '1GHz'))
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# Create a seperate clock domain for components that should run at
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# CPUs frequency
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system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
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for cpu in cpus:
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# create the interrupt controller
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cpu.createInterruptController()
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cpu.connectBus(system.membus)
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# All cpus are associated with cpu_clk_domain
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cpu.clk_domain = system.cpu_clk_domain
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# connect memory to membus
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system.physmem.port = system.membus.mem_side_ports
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# Connect the system port for loading of binaries etc
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system.system_port = system.membus.cpu_side_ports
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# -----------------------
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# run simulation
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# -----------------------
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root = Root(full_system = False, system = system)
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root.system.mem_mode = 'timing'
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