tests: Replace master/slave terminology from tests scripts

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Id7aafc082c7e4cfc977e807141e63a3feb5a6348
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52863
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

tests/configs/gpu-randomtest-ruby.py

@@ -125,11 +125,11 @@ for ruby_port in system.ruby._cpu_ports:
     # Tie the ruby tester ports to the ruby cpu read and write ports
     #
     if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
-        tester.cpuInstDataPort = ruby_port.slave
+        tester.cpuInstDataPort = ruby_port.in_ports
     elif ruby_port.support_data_reqs:
-        tester.cpuDataPort = ruby_port.slave
+        tester.cpuDataPort = ruby_port.in_ports
     elif ruby_port.support_inst_reqs:
-        tester.cpuInstPort = ruby_port.slave
+        tester.cpuInstPort = ruby_port.in_ports
 
     # Do not automatically retry stalled Ruby requests
     ruby_port.no_retry_on_stall = True

tests/configs/gpu-ruby.py

@@ -305,7 +305,7 @@ cpu.connectAllPorts(
     system.ruby._cpu_ports[0].in_ports,
     system.ruby._cpu_ports[0].in_ports,
     system.ruby._cpu_ports[0].interrupt_out_port)
-system.ruby._cpu_ports[0].mem_master_port = system.piobus.slave
+system.ruby._cpu_ports[0].mem_request_port = system.piobus.cpu_side_ports
 
 # attach CU ports to Ruby
 # Because of the peculiarities of the CP core, you may have 1 CPU but 2
@@ -338,8 +338,8 @@ gpu_port_idx = gpu_port_idx + 1
 assert(args.num_cp == 0)
 
 # connect dispatcher to the system.piobus
-dispatcher.pio = system.piobus.master
-dispatcher.dma = system.piobus.slave
+dispatcher.pio = system.piobus.mem_side_ports
+dispatcher.dma = system.piobus.cpu_side_ports
 
 ################# Connect the CPU and GPU via GPU Dispatcher ###################
 # CPU rings the GPU doorbell to notify a pending task

tests/configs/memtest-filter.py

@@ -50,10 +50,10 @@ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
 system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain,
                         snoop_filter = SnoopFilter())
 system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.cpu_side = system.toL2Bus.mem_side_ports
 
 # connect l2c to membus
-system.l2c.mem_side = system.membus.slave
+system.l2c.mem_side = system.membus.cpu_side_ports
 
 # add L1 caches
 for cpu in cpus:
@@ -61,12 +61,12 @@ for cpu in cpus:
     cpu.clk_domain = system.cpu_clk_domain
     cpu.l1c = L1Cache(size = '32kB', assoc = 4)
     cpu.l1c.cpu_side = cpu.port
-    cpu.l1c.mem_side = system.toL2Bus.slave
+    cpu.l1c.mem_side = system.toL2Bus.cpu_side_ports
 
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
 
 # connect memory to membus
-system.physmem.port = system.membus.master
+system.physmem.port = system.membus.mem_side_ports
 
 
 # -----------------------

tests/configs/memtest-ruby.py

@@ -100,7 +100,7 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
      # Tie the cpu port to the ruby cpu ports and
      # physmem, respectively
      #
-     cpus[i].port = ruby_port.slave
+     cpus[i].port = ruby_port.in_ports
 
      #
      # Since the memtester is incredibly bursty, increase the deadlock

tests/configs/memtest.py

@@ -49,10 +49,10 @@ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
 
 system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
 system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.cpu_side = system.toL2Bus.mem_side_ports
 
 # connect l2c to membus
-system.l2c.mem_side = system.membus.slave
+system.l2c.mem_side = system.membus.cpu_side_ports
 
 # add L1 caches
 for cpu in cpus:
@@ -60,12 +60,12 @@ for cpu in cpus:
     cpu.clk_domain = system.cpu_clk_domain
     cpu.l1c = L1Cache(size = '32kB', assoc = 4)
     cpu.l1c.cpu_side = cpu.port
-    cpu.l1c.mem_side = system.toL2Bus.slave
+    cpu.l1c.mem_side = system.toL2Bus.cpu_side_ports
 
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
 
 # connect memory to membus
-system.physmem.port = system.membus.master
+system.physmem.port = system.membus.mem_side_ports
 
 
 # -----------------------

tests/configs/o3-timing-mp-ruby.py

@@ -50,10 +50,10 @@ for cpu in cpus:
     cpu.clk_domain = system.cpu_clk_domain
 
 # connect memory to membus
-system.physmem.port = system.membus.master
+system.physmem.port = system.membus.mem_side_ports
 
 # Connect the system port for loading of binaries etc
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
 
 # -----------------------
 # run simulation

tests/configs/o3-timing-ruby.py

@@ -42,12 +42,12 @@ system = System(cpu = cpu,
 # CPUs frequency
 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
 
-system.physmem.port = system.membus.master
+system.physmem.port = system.membus.mem_side_ports
 # create the interrupt controller
 cpu.createInterruptController()
 cpu.connectBus(system.membus)
 
 # Connect the system port for loading of binaries etc
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
 
 root = Root(full_system = False, system = system)

tests/configs/pc-simple-timing-ruby.py

@@ -72,7 +72,7 @@ system.ruby.clk_domain = SrcClockDomain(clock = args.ruby_clock,
 
 # Connect the ruby io port to the PIO bus,
 # assuming that there is just one such port.
-system.iobus.master = system.ruby._io_port.slave
+system.iobus.mem_side_ports = system.ruby._io_port.in_ports
 
 for (i, cpu) in enumerate(system.cpu):
     # create the interrupt controller

tests/configs/rubytest-ruby.py

@@ -107,11 +107,11 @@ for ruby_port in system.ruby._cpu_ports:
     # Tie the ruby tester ports to the ruby cpu read and write ports
     #
     if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
-        tester.cpuInstDataPort = ruby_port.slave
+        tester.cpuInstDataPort = ruby_port.in_ports
     elif ruby_port.support_data_reqs:
-        tester.cpuDataPort = ruby_port.slave
+        tester.cpuDataPort = ruby_port.in_ports
     elif ruby_port.support_inst_reqs:
-        tester.cpuInstPort = ruby_port.slave
+        tester.cpuInstPort = ruby_port.in_ports
 
     # Do not automatically retry stalled Ruby requests
     ruby_port.no_retry_on_stall = True

tests/configs/simple-atomic-mp-ruby.py

@@ -48,10 +48,10 @@ for cpu in cpus:
     cpu.clk_domain = system.cpu_clk_domain
 
 # connect memory to membus
-system.physmem.port = system.membus.master
+system.physmem.port = system.membus.mem_side_ports
 
 # Connect the system port for loading of binaries etc
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
 
 # -----------------------
 # run simulation

tests/configs/t1000-simple-atomic.py

@@ -50,7 +50,7 @@ cpu.connectBus(system.membus)
 system.physmem = [SimpleMemory(range = r)
                   for r in system.mem_ranges]
 for i in range(len(system.physmem)):
-    system.physmem[i].port = system.membus.master
+    system.physmem[i].port = system.membus.mem_side_ports
 
 root = Root(full_system=True, system=system)
 

tests/gem5/configs/base_config.py

@@ -108,8 +108,8 @@ class BaseSystem(object, metaclass=ABCMeta):
         system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain)
         system.l2c = L2Cache(clk_domain=system.cpu_clk_domain,
                              size='4MB', assoc=8)
-        system.l2c.cpu_side = system.toL2Bus.master
-        system.l2c.mem_side = system.membus.slave
+        system.l2c.cpu_side = system.toL2Bus.mem_side_ports
+        system.l2c.mem_side = system.membus.cpu_side_ports
         return system.toL2Bus
 
     def init_cpu(self, system, cpu, sha_bus):
@@ -250,8 +250,8 @@ class BaseSESystem(BaseSystem):
                         mem_mode = self.mem_mode,
                         multi_thread = (self.num_threads > 1))
         if not self.use_ruby:
-            system.system_port = system.membus.slave
-        system.physmem.port = system.membus.master
+            system.system_port = system.membus.cpu_side_ports
+        system.physmem.port = system.membus.mem_side_ports
         self.init_system(system)
         return system
 
@@ -293,7 +293,7 @@ class BaseFSSystem(BaseSystem):
         if self.use_ruby:
             # Connect the ruby io port to the PIO bus,
             # assuming that there is just one such port.
-            system.iobus.master = system.ruby._io_port.slave
+            system.iobus.mem_side_ports = system.ruby._io_port.in_ports
         else:
             # create the memory controllers and connect them, stick with
             # the physmem name to avoid bumping all the reference stats
@@ -308,12 +308,12 @@ class BaseFSSystem(BaseSystem):
                 system.physmem = [self.mem_class(range = r)
                                   for r in system.mem_ranges]
             for i in range(len(system.physmem)):
-                system.physmem[i].port = system.membus.master
+                system.physmem[i].port = system.membus.mem_side_ports
 
             # create the iocache, which by default runs at the system clock
             system.iocache = IOCache(addr_ranges=system.mem_ranges)
-            system.iocache.cpu_side = system.iobus.master
-            system.iocache.mem_side = system.membus.slave
+            system.iocache.cpu_side = system.iobus.mem_side_ports
+            system.iocache.mem_side = system.membus.cpu_side_ports
 
     def create_root(self):
         system = self.create_system()

tests/gem5/cpu_tests/run.py

@@ -43,7 +43,7 @@ class L1Cache(Cache):
 
     def connectBus(self, bus):
         """Connect this cache to a memory-side bus"""
-        self.mem_side = bus.slave
+        self.mem_side = bus.cpu_side_ports
 
     def connectCPU(self, cpu):
         """Connect this cache's port to a CPU-side port
@@ -83,10 +83,10 @@ class L2Cache(Cache):
     tgts_per_mshr = 12
 
     def connectCPUSideBus(self, bus):
-        self.cpu_side = bus.master
+        self.cpu_side = bus.mem_side_ports
 
     def connectMemSideBus(self, bus):
-        self.mem_side = bus.slave
+        self.mem_side = bus.cpu_side_ports
 
 
 class MySimpleMemory(SimpleMemory):
@@ -134,8 +134,8 @@ system.cpu = valid_cpu[args.cpu]()
 
 if args.cpu == "AtomicSimpleCPU":
     system.membus = SystemXBar()
-    system.cpu.icache_port = system.membus.slave
-    system.cpu.dcache_port = system.membus.slave
+    system.cpu.icache_port = system.membus.cpu_side_ports
+    system.cpu.dcache_port = system.membus.cpu_side_ports
 else:
     system.cpu.l1d = L1DCache()
     system.cpu.l1i = L1ICache()
@@ -151,14 +151,14 @@ else:
 
 system.cpu.createInterruptController()
 if m5.defines.buildEnv['TARGET_ISA'] == "x86":
-    system.cpu.interrupts[0].pio = system.membus.master
-    system.cpu.interrupts[0].int_master = system.membus.slave
-    system.cpu.interrupts[0].int_slave = system.membus.master
+    system.cpu.interrupts[0].pio = system.membus.mem_side_ports
+    system.cpu.interrupts[0].int_master = system.membus.cpu_side_ports
+    system.cpu.interrupts[0].int_slave = system.membus.mem_side_ports
 
 system.mem_ctrl = valid_mem[args.mem]()
 system.mem_ctrl.range = system.mem_ranges[0]
-system.mem_ctrl.port = system.membus.master
-system.system_port = system.membus.slave
+system.mem_ctrl.port = system.membus.mem_side_ports
+system.system_port = system.membus.cpu_side_ports
 
 process = Process()
 process.cmd = [args.binary]

tests/gem5/m5threads_test_atomic/atomic_system.py

@@ -62,7 +62,7 @@ root.system.membus = SystemXBar()
 root.system.membus.badaddr_responder = BadAddr()
 root.system.membus.default = root.system.membus.badaddr_responder.pio
 
-root.system.system_port = root.system.membus.slave
+root.system.system_port = root.system.membus.cpu_side_ports
 
 process = Process(executable = args.cmd,
                   cmd = [args.cmd, str(args.num_cores)])
@@ -96,7 +96,7 @@ for cpu in root.system.cpu:
 
 root.system.mem_ctrl = DDR3_1600_8x8()
 root.system.mem_ctrl.range = root.system.mem_ranges[0]
-root.system.mem_ctrl.port = root.system.membus.master
+root.system.mem_ctrl.port = root.system.membus.mem_side_ports
 
 m5.instantiate()
 exit_event = m5.simulate()

tests/gem5/m5threads_test_atomic/caches.py

@@ -56,7 +56,7 @@ class L1Cache(PrefetchCache):
 
     def connectBus(self, bus):
         """Connect this cache to a memory-side bus"""
-        self.mem_side = bus.slave
+        self.mem_side = bus.cpu_side_ports
 
     def connectCPU(self, cpu):
         """Connect this cache's port to a CPU-side port
@@ -106,7 +106,7 @@ class L2Cache(PrefetchCache):
         super(L2Cache, self).__init__(opts)
 
     def connectCPUSideBus(self, bus):
-        self.cpu_side = bus.master
+        self.cpu_side = bus.mem_side_ports
 
     def connectMemSideBus(self, bus):
-        self.mem_side = bus.slave
+        self.mem_side = bus.cpu_side_ports

tests/gem5/memory/memtest-run.py

@@ -50,10 +50,10 @@ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
 
 system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
 system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.cpu_side = system.toL2Bus.mem_side_ports
 
 # connect l2c to membus
-system.l2c.mem_side = system.membus.slave
+system.l2c.mem_side = system.membus.cpu_side_ports
 
 # add L1 caches
 for cpu in cpus:
@@ -61,12 +61,12 @@ for cpu in cpus:
     cpu.clk_domain = system.cpu_clk_domain
     cpu.l1c = L1Cache(size = '32kB', assoc = 4)
     cpu.l1c.cpu_side = cpu.port
-    cpu.l1c.mem_side = system.toL2Bus.slave
+    cpu.l1c.mem_side = system.toL2Bus.cpu_side_ports
 
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
 
 # connect memory to membus
-system.physmem.port = system.membus.master
+system.physmem.port = system.membus.mem_side_ports
 
 
 # -----------------------

tests/gem5/memory/simple-run.py

@@ -76,14 +76,14 @@ system.monitor.trace = MemTraceProbe(trace_file = "monitor.ptrc.gz")
 system.monitor.stackdist = StackDistProbe(verify = True)
 
 # connect the traffic generator to the bus via a communication monitor
-system.cpu.port = system.monitor.slave
-system.monitor.master = system.membus.slave
+system.cpu.port = system.monitor.cpu_side_port
+system.monitor.mem_side_port = system.membus.cpu_side_ports
 
 # connect the system port even if it is not used in this example
-system.system_port = system.membus.slave
+system.system_port = system.membus.cpu_side_ports
 
 # connect memory to the membus
-system.physmem.port = system.membus.master
+system.physmem.port = system.membus.mem_side_ports
 
 # -----------------------
 # run simulation