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gem5/src/dev
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Gabe Black ae390c629f arch: Make a base class for Interrupts. 
That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.

Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-19 01:45:48 +00:00
..
alpha
arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.
2019-05-29 04:23:46 +00:00
arm
dev-arm: Check for gem5 extensions in GicV2
2019-10-18 22:44:26 +00:00
i2c
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
mips
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
net
dev, misc: Fixing "may be used unitialized" compilation error
2019-10-03 21:11:08 +00:00
pci
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
ps2
ps2: Unify constant names
2018-04-17 12:24:17 +00:00
serial
dev: Terminal output's dump name conflicts
2019-09-19 21:46:32 +00:00
sparc
sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.
2019-04-30 18:52:13 +00:00
storage
arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.
2019-05-18 10:20:20 +00:00
virtio
dev: Fix segmentation fault in VirtIOBlock
2019-09-06 16:14:30 +00:00
x86
arch: Make a base class for Interrupts.
2019-10-19 01:45:48 +00:00
baddev.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
baddev.hh
AddrRange: Transition from Range<T> to AddrRange
2012-09-19 06:15:44 -04:00
BadDevice.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
Device.py
dev: Enable DTB IOMMU binding with a DMA object
2019-09-13 08:14:24 +00:00
dma_device.cc
dev: StreamID generation in DMA device
2019-05-03 08:38:12 +00:00
dma_device.hh
dev: StreamID generation in DMA device
2019-05-03 08:38:12 +00:00
intel_8254_timer.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
intel_8254_timer.hh
sim: Refactor the serialization base class
2015-07-07 09:51:03 +01:00
intpin.cc
dev: Generalize the x86 int source/sink pins.
2019-09-12 20:36:39 +00:00
intpin.hh
dev: Generalize the x86 int source/sink pins.
2019-09-12 20:36:39 +00:00
IntPin.py
dev: Generalize the x86 int source/sink pins.
2019-09-12 20:36:39 +00:00
io_device.cc
dev: Templatize PioPort.
2019-09-04 02:30:01 +00:00
io_device.hh
dev: Templatize PioPort.
2019-09-04 02:30:01 +00:00
isa_fake.cc
dev: Explicitly specify the endianness for packet accessors.
2018-10-17 20:17:44 +00:00
isa_fake.hh
AddrRange: Transition from Range<T> to AddrRange
2012-09-19 06:15:44 -04:00
mc146818.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
mc146818.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
pixelpump.cc
dev: Add support for single-pass scan out in the PixelPump
2017-03-07 11:14:28 +00:00
pixelpump.hh
dev: Add support for single-pass scan out in the PixelPump
2017-03-07 11:14:28 +00:00
platform.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
platform.hh
dev: Rewrite PCI host functionality
2015-12-05 00:11:24 +00:00
Platform.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
rtcreg.h
dev: Clean up MC146818 register (A & B) handling
2013-06-03 12:28:41 +02:00
SConscript
dev: Generalize the x86 int source/sink pins.
2019-09-12 20:36:39 +00:00