Giacomo Travaglini b6a08919e9 sim: Replace any getDTBPtr/getITBPtr usage ...

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: Ibd78bef263d186889f4533583ff30f46a0a8643f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34981
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

2020-10-27 16:45:33 +00:00

..

arch

arch-x86: Replace any getDTBPtr/getITBPtr usage

2020-10-27 14:56:39 +00:00

base

misc: Replace enable_if<>::type with enable_if_t<>.

2020-10-23 12:59:59 +00:00

cpu

cpu: Remove unused demapInstPage and demapDataPage

2020-10-21 09:33:39 +00:00

dev

dev-arm: Fix VExpressFastmodel interrupt configs

2020-10-23 04:31:48 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

gpu: Use X86ISA instead of TheISA in src/gpu-compute.

2020-10-26 20:32:43 +00:00

kern

misc: Update attribute syntax, and reorganize compiler.hh.

2020-09-28 21:52:59 +00:00

learning_gem5

misc: Standardize the way create() constructs SimObjects.

2020-10-14 12:06:44 +00:00

mem

mem: Replace any getDTBPtr/getITBPtr usage

2020-10-26 09:20:08 +00:00

proto

misc: Use the protobuf version to choose between ByteSize(Long).

2020-04-29 21:46:11 +00:00

python

python: Add support for Proxy division

2020-10-23 21:49:11 +00:00

sim

sim: Replace any getDTBPtr/getITBPtr usage

2020-10-27 16:45:33 +00:00

systemc

misc: Standardize the way create() constructs SimObjects.

2020-10-14 12:06:44 +00:00

unittest

base: Make the Value stat's functor method accept lambdas.

2020-09-01 21:57:34 +00:00

Doxyfile

misc: Changed gem5 version info for gem5 20.2 dev

2020-10-01 17:37:53 +00:00

SConscript

scons: Simplify arch enum generation

2020-09-07 08:42:07 +00:00