Change-Id: I4df2557c71e38cc4e3a485b0e590e85eb45de8b6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33553 Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
219 lines
6.1 KiB
C++
219 lines
6.1 KiB
C++
/*
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* Copyright (c) 2018, 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mem/mem_delay.hh"
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#include "params/MemDelay.hh"
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#include "params/SimpleMemDelay.hh"
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MemDelay::MemDelay(const MemDelayParams *p)
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: ClockedObject(p),
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requestPort(name() + "-mem_side_port", *this),
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responsePort(name() + "-cpu_side_port", *this),
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reqQueue(*this, requestPort),
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respQueue(*this, responsePort),
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snoopRespQueue(*this, requestPort)
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{
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}
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void
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MemDelay::init()
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{
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if (!responsePort.isConnected() || !requestPort.isConnected())
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fatal("Memory delay is not connected on both sides.\n");
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}
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Port &
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MemDelay::getPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "mem_side_port") {
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return requestPort;
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} else if (if_name == "cpu_side_port") {
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return responsePort;
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} else {
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return ClockedObject::getPort(if_name, idx);
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}
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}
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bool
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MemDelay::trySatisfyFunctional(PacketPtr pkt)
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{
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return responsePort.trySatisfyFunctional(pkt) ||
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requestPort.trySatisfyFunctional(pkt);
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}
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MemDelay::RequestPort::RequestPort(const std::string &_name, MemDelay &_parent)
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: QueuedRequestPort(_name, &_parent,
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_parent.reqQueue, _parent.snoopRespQueue),
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parent(_parent)
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{
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}
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bool
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MemDelay::RequestPort::recvTimingResp(PacketPtr pkt)
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{
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// technically the packet only reaches us after the header delay,
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// and typically we also need to deserialise any payload
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const Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
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pkt->headerDelay = pkt->payloadDelay = 0;
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const Tick when = curTick() + parent.delayResp(pkt) + receive_delay;
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parent.responsePort.schedTimingResp(pkt, when);
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return true;
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}
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void
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MemDelay::RequestPort::recvFunctionalSnoop(PacketPtr pkt)
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{
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if (parent.trySatisfyFunctional(pkt)) {
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pkt->makeResponse();
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} else {
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parent.responsePort.sendFunctionalSnoop(pkt);
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}
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}
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Tick
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MemDelay::RequestPort::recvAtomicSnoop(PacketPtr pkt)
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{
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const Tick delay = parent.delaySnoopResp(pkt);
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return delay + parent.responsePort.sendAtomicSnoop(pkt);
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}
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void
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MemDelay::RequestPort::recvTimingSnoopReq(PacketPtr pkt)
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{
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parent.responsePort.sendTimingSnoopReq(pkt);
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}
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MemDelay::ResponsePort::
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ResponsePort(const std::string &_name, MemDelay &_parent)
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: QueuedResponsePort(_name, &_parent, _parent.respQueue),
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parent(_parent)
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{
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}
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Tick
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MemDelay::ResponsePort::recvAtomic(PacketPtr pkt)
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{
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const Tick delay = parent.delayReq(pkt) + parent.delayResp(pkt);
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return delay + parent.requestPort.sendAtomic(pkt);
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}
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bool
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MemDelay::ResponsePort::recvTimingReq(PacketPtr pkt)
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{
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// technically the packet only reaches us after the header
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// delay, and typically we also need to deserialise any
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// payload
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Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
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pkt->headerDelay = pkt->payloadDelay = 0;
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const Tick when = curTick() + parent.delayReq(pkt) + receive_delay;
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parent.requestPort.schedTimingReq(pkt, when);
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return true;
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}
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void
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MemDelay::ResponsePort::recvFunctional(PacketPtr pkt)
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{
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if (parent.trySatisfyFunctional(pkt)) {
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pkt->makeResponse();
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} else {
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parent.requestPort.sendFunctional(pkt);
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}
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}
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bool
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MemDelay::ResponsePort::recvTimingSnoopResp(PacketPtr pkt)
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{
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const Tick when = curTick() + parent.delaySnoopResp(pkt);
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parent.requestPort.schedTimingSnoopResp(pkt, when);
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return true;
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}
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SimpleMemDelay::SimpleMemDelay(const SimpleMemDelayParams *p)
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: MemDelay(p),
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readReqDelay(p->read_req),
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readRespDelay(p->read_resp),
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writeReqDelay(p->write_req),
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writeRespDelay(p->write_resp)
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{
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}
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Tick
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SimpleMemDelay::delayReq(PacketPtr pkt)
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{
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if (pkt->isRead()) {
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return readReqDelay;
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} else if (pkt->isWrite()) {
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return writeReqDelay;
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} else {
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return 0;
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}
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}
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Tick
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SimpleMemDelay::delayResp(PacketPtr pkt)
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{
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if (pkt->isRead()) {
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return readRespDelay;
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} else if (pkt->isWrite()) {
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return writeRespDelay;
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} else {
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return 0;
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}
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}
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SimpleMemDelay *
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SimpleMemDelayParams::create()
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{
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return new SimpleMemDelay(this);
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}
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