073c32be2c
The TARGET_ISA variable would let you select one ISA from a list of possible ISAs. That has now been replaced with USE_ARM_ISA, USE_X86_ISA, etc, variables which are boolean on or off. That will allow any number of ISAs to be enabled or disabled individually. Enabling something other than exactly one of these will probably prevent you from getting a working gem5 binary, but those problems are being addressed in other, parallel change series. I decided to use the USE_ prefix since it was consistent with most other on/off variables we have in gem5. One noteable exception is the BUILD_GPU setting which, you could convincingly argue, is a better prefix than USE_. Another option would be to use CONFIG_, in anticipation of using a kconfig style config mechanism in gem5. It seemed premature to start using a CONFIG_ prefix here, and if we decide to switch to some other prefix like BUILD_, it should be a purposeful choice and not something somebody just starts using. Change-Id: I90fef2835aa4712782e6c1313fbf564d0ed45538 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52491 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Gabe Black <gabe.black@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
89 lines
3.4 KiB
Python
89 lines
3.4 KiB
Python
# Copyright (c) 2017, University of Kaiserslautern
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Author: Éder F. Zulian
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import sys
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import argparse
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import m5
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from m5.objects import *
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from m5.util import *
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from gem5.runtime import get_runtime_isa
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addToPath("../")
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from common import MemConfig
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from common import HMC
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pd = "Simple 'hello world' example using HMC as main memory"
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parser = argparse.ArgumentParser(description=pd)
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HMC.add_options(parser)
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options = parser.parse_args()
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# create the system we are going to simulate
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system = System()
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# use timing mode for the interaction between requestor-responder ports
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system.mem_mode = "timing"
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# set the clock frequency of the system
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clk = "1GHz"
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vd = VoltageDomain(voltage="1V")
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system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
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# create a simple CPU
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system.cpu = TimingSimpleCPU()
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# config memory system
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MemConfig.config_mem(options, system)
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# hook the CPU ports up to the membus
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system.cpu.icache_port = system.membus.cpu_side_ports
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system.cpu.dcache_port = system.membus.cpu_side_ports
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# create the interrupt controller for the CPU and connect to the membus
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system.cpu.createInterruptController()
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# connect special port in the system to the membus. This port is a
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# functional-only port to allow the system to read and write memory.
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system.system_port = system.membus.cpu_side_ports
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# get ISA for the binary to run.
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isa = get_runtime_isa()
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# run 'hello' and use the compiled ISA to find the binary
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binary = "tests/test-progs/hello/bin/" + isa.name.lower() + "/linux/hello"
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# create a process for a simple "Hello World" application
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process = Process()
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# cmd is a list which begins with the executable (like argv)
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process.cmd = [binary]
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# set the system workload
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system.workload = SEWorkload.init_compatible(binary)
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# set the cpu workload
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system.cpu.workload = process
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# create thread contexts
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system.cpu.createThreads()
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# set up the root SimObject
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root = Root(full_system=False, system=system)
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m5.instantiate()
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m5.simulate()
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