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ae5a51994c112d04bfe0eb84189ca9ec5a46102e
gem5/src/mem/cache
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Hoa Nguyen 91d1a5deb5 mem-cache: Fix bug in classic cache while clflush 
This change, https://github.com/gem5/gem5/pull/205, mistakenly
allocates write buffer for clflush instruction when there's a
cache miss. However, clflush in gem5 is not a write instruction.
Thus, the cache should allocate miss buffer in this case.

Change-Id: I9c1c9b841159c4420567e9c929e71e4aa27d5c28
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-09-08 18:16:10 +00:00
..
compressors
mem-cache: Remove the Encoder namespace
2023-01-17 09:16:20 +00:00
prefetch
mem-cache: Remove the Prefetcher namespace
2023-01-17 09:16:20 +00:00
replacement_policies
mem-cache: Remove the ReplacementPolicy namespace
2023-01-17 09:16:20 +00:00
tags
mem-cache: De-virtualize forEachBlk() in tags
2023-06-08 00:26:02 +00:00
base.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
base.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
cache_blk.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cache_blk.hh
mem-cache: Ensure all fields of the CacheBlk class are initialized.
2021-11-04 22:53:51 +00:00
cache.cc
mem-cache: Fix bug in classic cache while clflush
2023-09-08 18:16:10 +00:00
cache.hh
mem,gpu-compute: Stop using the GEM5_NO_DISCARD macro.
2021-07-24 21:57:04 +00:00
Cache.py
python: Fix multiline quotes in a single line
2022-11-29 23:44:38 +00:00
mshr_queue.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mshr_queue.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mshr.cc
mem-cache: masked writes are not whole-line writes
2023-01-17 10:09:56 +00:00
mshr.hh
mem: implement x86 locked accesses in timing-mode classic cache
2022-01-17 15:15:24 +00:00
noncoherent_cache.cc
mem-cache: Set prefetch bit if the blk comes from Prefetch only.
2021-12-22 01:02:22 +00:00
noncoherent_cache.hh
mem,gpu-compute: Stop using the GEM5_NO_DISCARD macro.
2021-07-24 21:57:04 +00:00
queue_entry.hh
mem: implement x86 locked accesses in timing-mode classic cache
2022-01-17 15:15:24 +00:00
queue.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
SConscript
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
write_queue_entry.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
write_queue_entry.hh
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
write_queue.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
write_queue.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00