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gem5/src/arch/arm
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Fernando Endo 6c72c35519 cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass 
Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to
Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which
distinguishes writes to the INT and FP register banks.
Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72,
where the "latency" of FMADD is 3 if the next instruction is a FMADD and
has only the augend to destination dependency, otherwise it's 7 cycles.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-10-15 14:58:45 -05:00
..
freebsd
base: add symbol support for dynamic libraries
2016-03-17 10:34:27 -07:00
insts
isa,arm: Add missing AArch32 FP instructions
2016-10-13 19:22:10 +01:00
isa
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
2016-10-15 14:58:45 -05:00
kvm
kvm, arm: Make GIC interrupt lines configurable
2016-04-27 15:34:48 +01:00
linux
kern, arm: Dump dmesg on kernel panic/oops
2016-06-20 14:39:49 +01:00
ArmInterrupts.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
ArmISA.py
arm: enable EL2 support
2016-08-02 10:38:01 +01:00
ArmNativeTrace.py
cpu: Put all CPU instruction tracers in a single file
2015-01-25 07:22:17 -05:00
ArmPMU.py
arm: Add helper methods to setup architected PMU events
2014-10-16 05:49:42 -04:00
ArmSystem.py
kern, arm: Dump dmesg on kernel panic/oops
2016-06-20 14:39:49 +01:00
ArmTLB.py
arm: Share a port for the two table walker objects
2015-03-02 04:00:42 -05:00
ccregs.hh
arm: use condition code registers for ARM ISA
2014-04-29 16:05:02 -05:00
decoder.cc
isa: Add parameter to pick different decoder inside ISA
2015-10-09 14:50:54 -05:00
decoder.hh
isa: Add parameter to pick different decoder inside ISA
2015-10-09 14:50:54 -05:00
faults.cc
arm: correctly assign faulting IPA's to HPFAR_EL2
2016-08-02 10:38:03 +01:00
faults.hh
arm: Add AArch64 hypervisor call instruction 'hvc'
2016-08-02 10:38:02 +01:00
interrupts.cc
arm: Fix secure state checking in various places
2016-08-02 10:38:02 +01:00
interrupts.hh
arm: Fix secure state checking in various places
2016-08-02 10:38:02 +01:00
intregs.hh
arm: ISA X31 destination register fix
2014-09-03 07:42:43 -04:00
isa_device.cc
arm: Add support for filtering in the PMU
2014-12-23 09:31:17 -05:00
isa_device.hh
misc: Remove redundant compiler-specific defines
2015-10-12 04:07:59 -04:00
isa_traits.hh
arch: Cleanup unused ISA traits constants
2014-09-03 07:42:21 -04:00
isa.cc
cpu, arch: fix the type used for the request flags
2016-08-15 12:00:35 +01:00
isa.hh
arm: enable EL2 support
2016-08-02 10:38:01 +01:00
kernel_stats.hh
Make commenting on close namespace brackets consistent.
2011-01-03 14:35:43 -08:00
locked_mem.hh
mem, cpu: Add assertions to snoop invalidation logic
2015-08-10 11:25:52 +01:00
microcode_rom.hh
arm: include missing file for arm
2009-04-21 15:40:26 -07:00
miscregs.cc
arm: warn not fail on use of missing miscreg CNTHCTL_EL2
2016-08-02 10:38:03 +01:00
miscregs.hh
arm: add stage2 translation support
2016-08-02 10:38:02 +01:00
mmapped_ipr.hh
arch: Add support for m5ops using mmapped IPRs
2013-09-30 12:20:43 +02:00
nativetrace.cc
arm: use condition code registers for ARM ISA
2014-04-29 16:05:02 -05:00
nativetrace.hh
ARM: Add vfpv3 support to native trace.
2011-05-04 20:38:26 -05:00
pagetable.hh
arm: Mark uninitialized new TLB entries as not valid
2016-06-20 15:51:31 +01:00
pmu.cc
arm,dev: remove PMU assertion hit on reset
2016-04-15 10:03:03 -05:00
pmu.hh
misc: Remove redundant compiler-specific defines
2015-10-12 04:07:59 -04:00
process.cc
base: support dynamic loading of Linux ELF objects in SE mode
2016-03-17 10:31:03 -07:00
process.hh
arm: Fixes based on UBSan and static analysis
2014-11-14 03:53:51 -05:00
pseudo_inst.hh
kvm, x86: Adding support for SE mode execution
2014-11-23 18:01:08 -08:00
registers.hh
revert 5af8f40d8f2c
2015-07-28 01:58:04 -05:00
remote_gdb.cc
arm: remote GDB: rationalize structure of register offsets
2015-12-18 15:12:07 -06:00
remote_gdb.hh
arm: remote GDB: rationalize structure of register offsets
2015-12-18 15:12:07 -06:00
SConscript
style: remove trailing whitespace
2016-02-06 17:21:18 -08:00
SConsopts
arm: add ARM support to M5
2009-04-05 18:53:15 -07:00
stacktrace.cc
style: remove trailing whitespace
2016-02-06 17:21:18 -08:00
stacktrace.hh
arch: Use const StaticInstPtr references where possible
2014-09-27 09:08:36 -04:00
stage2_lookup.cc
arm: Check TLB stage 2 permissions in AArch64
2016-08-02 10:38:03 +01:00
stage2_lookup.hh
sim: Move the BaseTLB to src/arch/generic/
2015-02-11 10:23:27 -05:00
stage2_mmu.cc
sim: Decouple draining from the SimObject hierarchy
2015-07-07 09:51:05 +01:00
stage2_mmu.hh
sim: Decouple draining from the SimObject hierarchy
2015-07-07 09:51:05 +01:00
system.cc
arm: Make EL checks available in SE mode
2016-05-26 17:33:38 +01:00
system.hh
arm: enable EL2 support
2016-08-02 10:38:01 +01:00
table_walker.cc
arm: refactor page table walking
2016-08-02 10:38:03 +01:00
table_walker.hh
arm: refactor page table walking
2016-08-02 10:38:03 +01:00
tlb.cc
cpu, arch: fix the type used for the request flags
2016-08-15 12:00:35 +01:00
tlb.hh
arm: Add TLBI instruction for stage 2 IPA's
2016-08-02 10:38:03 +01:00
types.hh
arch: get rid of unused LargestRead typedef
2016-01-17 18:27:46 -08:00
utility.cc
arm: Fix trapping to Hypervisor during MSR/MRS read/write
2016-08-02 10:38:03 +01:00
utility.hh
arm: Fix trapping to Hypervisor during MSR/MRS read/write
2016-08-02 10:38:03 +01:00
vtophys.cc
mem: Remove threadId from memory request class
2016-04-07 09:30:20 -05:00
vtophys.hh
gcc: Clean-up of non-C++0x compliant code, first steps
2012-03-19 06:36:09 -04:00