Alexandru Dutu adbaa4dfde kvm, x86: Adding support for SE mode execution ...

This patch adds methods in KvmCPU model to handle KVM exits caused by syscall
instructions and page faults. These types of exits will be encountered if
KvmCPU is run in SE mode.

2014-11-23 18:01:08 -08:00

..

insts

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

isa

arch: Use shared_ptr for all Faults

2014-10-16 05:49:51 -04:00

linux

sim: revert 6709bbcf564d

2014-10-22 15:59:57 -05:00

decoder.cc

ISA,CPU: Generalize and split out the components of the decode cache.

2012-05-26 13:45:12 -07:00

decoder.hh

x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch

2013-01-22 00:10:10 -06:00

faults.hh

Faults: Replace calls to genMachineCheckFault with M5PanicFault.

2011-09-27 00:24:43 -07:00

interrupts.cc

SE/FS: Build the Interrupt objects in SE mode.

2011-10-09 00:15:50 -07:00

interrupts.hh

SE/FS: Build the Interrupt objects in SE mode.

2011-10-09 00:15:50 -07:00

isa_traits.hh

arch: Cleanup unused ISA traits constants

2014-09-03 07:42:21 -04:00

isa.cc

arch: Make the ISA class inherit from SimObject

2013-01-07 13:05:35 -05:00

isa.hh

arch: Make all register index flattening const

2014-01-24 15:29:30 -06:00

kernel_stats.hh

Power: Add a stub kernel_stats.hh.

2011-11-13 12:40:15 -08:00

locked_mem.hh

cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.

2014-01-24 15:29:30 -06:00

microcode_rom.hh

Make commenting on close namespace brackets consistent.

2011-01-03 14:35:43 -08:00

miscregs.hh

Make commenting on close namespace brackets consistent.

2011-01-03 14:35:43 -08:00

mmapped_ipr.hh

arch: Add support for m5ops using mmapped IPRs

2013-09-30 12:20:43 +02:00

pagetable.cc

Make commenting on close namespace brackets consistent.

2011-01-03 14:35:43 -08:00

pagetable.hh

SE/FS: Get rid of includes of config/full_system.hh.

2011-11-18 02:20:22 -08:00

PowerInterrupts.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

PowerISA.py

arch: Make the ISA class inherit from SimObject

2013-01-07 13:05:35 -05:00

PowerTLB.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

process.cc

arch: Cleanup unused ISA traits constants

2014-09-03 07:42:21 -04:00

process.hh

mem: adding architectural page table support for SE mode

2014-08-28 10:11:44 -05:00

pseudo_inst.hh

kvm, x86: Adding support for SE mode execution

2014-11-23 18:01:08 -08:00

registers.hh

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

remote_gdb.hh

Make commenting on close namespace brackets consistent.

2011-01-03 14:35:43 -08:00

SConscript

arch: teach ISA parser how to split code across files

2014-05-09 18:58:47 -04:00

SConsopts

POWER: Add support for the Power ISA

2009-10-27 09:24:39 -07:00

stacktrace.cc

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

stacktrace.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

tlb.cc

arch: Use shared_ptr for all Faults

2014-10-16 05:49:51 -04:00

tlb.hh

arch: Use shared_ptr for all Faults

2014-10-16 05:49:51 -04:00

types.hh

clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6

2012-04-14 05:43:31 -04:00

utility.cc

cpu: add a condition-code register class

2013-10-15 14:22:44 -04:00

utility.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

vtophys.cc

Implement Ali's review feedback.

2012-01-29 02:04:34 -08:00

vtophys.hh

Merge with main repository.

2012-01-30 21:07:57 -08:00