gem5/src/cpu at aba2eeaf8fba432ac5ee27a969543b9a92d485e1 - gem5

checker

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

memtest

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

o3

Fix typo so m5.fast will compile

2007-06-01 20:41:46 -07:00

ozone

Fix cut-n-pasto to make the path correct

2007-05-30 17:19:20 -07:00

simple

cast sizeof(MachInst) to Addr before generating a mask

2007-06-01 14:16:58 -04:00

trace

Rework the way SCons recurses into subdirectories, making it

2007-03-10 23:00:54 -08:00

activity.cc

make our code a little more standards compliant

2007-01-26 18:48:51 -05:00

activity.hh

Update copyright.

2006-06-07 16:02:55 -04:00

base_dyn_inst_impl.hh

Two fixes:

2007-03-23 11:33:08 -04:00

base_dyn_inst.hh

Get the "hard" SPARC instructions working in o3. I don't like that the IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.

2007-04-08 01:42:42 +00:00

base.cc

Add new EventWrapper constructor that takes a Tick value

2007-05-20 21:43:01 -07:00

base.hh

Merge zizzer.eecs.umich.edu:/bk/newmem

2007-03-15 02:52:51 +00:00

BaseCPU.py

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

cpu_models.py

Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.

2006-07-06 12:18:55 -04:00

cpuevent.cc

…

cpuevent.hh

Make SPARC checkpointing work

2007-01-30 18:25:39 -05:00

exec_context.hh

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

exetrace.cc

Fixed a compile error.

2007-04-10 01:52:38 +00:00

exetrace.hh

Add setData functions for the new Twin??_t types.

2007-03-07 17:46:06 +00:00

func_unit.cc

Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.

2006-06-16 17:52:15 -04:00

func_unit.hh

Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.

2006-06-16 17:52:15 -04:00

FuncUnit.py

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

inst_seq.hh

fixes so that M5 will compile under solaris

2006-11-04 21:41:01 -05:00

intr_control.cc

Implement Niagara I/O interface and rework interrupts

2007-03-03 17:22:47 -05:00

intr_control.hh

Implement Niagara I/O interface and rework interrupts

2007-03-03 17:22:47 -05:00

IntrControl.py

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

m5legion_interface.h

add fsr to the list of registers we are interested in

2007-01-30 18:27:04 -05:00

op_class.cc

…

op_class.hh

…

pc_event.cc

remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault

2007-03-12 17:23:08 -04:00

pc_event.hh

Added sim/host.hh for the Addr type.

2006-11-07 05:42:15 -05:00

profile.cc

…

profile.hh

Put the ProcessInfo and StackTrace objects into the ISA namespaces.

2006-11-08 00:52:04 -05:00

quiesce_event.cc

Add Quiesce trace flag to track CPU quiesce/wakeup events.

2006-10-21 23:32:14 -07:00

quiesce_event.hh

Update copyright.

2006-06-07 16:02:55 -04:00

SConscript

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

simple_thread.cc

Fixes for splash, may conflict with Korey's SMT work and doesn't support 03cpu yet.

2007-04-16 11:31:54 -04:00

simple_thread.hh

Remove unnecessary include of physical.hh.

2007-05-28 08:03:13 -07:00

smt.hh

…

static_inst.cc

Move all of the parameters of the Root SimObject so they are

2007-03-06 11:13:43 -08:00

static_inst.hh

Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.

2007-03-15 02:47:42 +00:00

thread_context.hh

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

thread_state.cc

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

thread_state.hh

Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.

2006-11-29 16:07:55 -05:00