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aa75b9a7a7489bf86c4e6d406ff612e596ddff96
gem5/src/arch
History
Korey Sewell aa75b9a7a7 merge mips fix and statetrace changes
2009-07-31 10:40:42 -04:00
..
alpha
Alpha: Missed a file in an earlier changeset.
2009-07-09 00:20:41 -07:00
arm
ARM: Mul and mla ignore the c and v flags, but we were setting them to 1.
2009-07-29 22:24:00 -07:00
mips
merge mips fix and statetrace changes
2009-07-31 10:40:42 -04:00
sparc
SPARC: Fix a minor compile bug in native trace on gcc > 4.1.
2009-07-25 15:14:00 -07:00
x86
CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
2009-07-19 23:54:56 -07:00
isa_parser.py
isa_parser: Get rid of the now unused ControlBitfieldOperand.
2009-07-20 20:20:17 -07:00
isa_specific.hh
style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
2008-09-10 14:26:15 -04:00
micro_asm_test.py
Add a second section to make sure the ROM is extended properly.
2007-05-31 22:21:21 +00:00
micro_asm.py
Microcode: Fix a silent typo error in the microcode assembler.
2008-10-09 00:07:38 -07:00
SConscript
Registers: Add a registers.hh file as an ISA switched header.
2009-07-08 23:02:21 -07:00
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