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ARM: Mul and mla ignore the c and v flags, but we were setting them to 1.

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Gabe Black
2009-07-29 22:24:00 -07:00
parent e09ae149af
commit 4971331b4f
1 changed files with 4 additions and 2 deletions
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6
src/arch/arm/isa/formats/pred.isa
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@@ -105,7 +105,8 @@ let {{
def getCcCode(flagtype):
icReg = icImm = iv = ''
if flagtype == "none":
icReg = icImm = iv = '1'
icReg = icImm = 'Cpsr<29:>'
iv = 'Cpsr<28:>'
elif flagtype == "add":
icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
iv = 'findOverflow(32, resTemp, Rn, op2)'
@@ -125,7 +126,8 @@ let {{
def getImmCcCode(flagtype):
ivValue = icValue = ''
if flagtype == "none":
icValue = ivValue = '1'
icValue = 'Cpsr<29:>'
ivValue = 'Cpsr<28:>'
elif flagtype == "add":
icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'