Korey Sewell a892af7b26 inorder: dont allow early loads ...

- loads were happening on same cycle as the address was generated which is slightly
unrealistic. Instead, force address generation to be on separate cycle from load
initiation
- also, mark the stages in a more traditional way (F-D-X-M-W)

2010-01-31 18:25:27 -05:00

..

arch

compile: compile on 32 bit hardware

2009-11-05 17:21:26 -08:00

base

build: need to include cstdio

2010-01-23 14:02:03 -08:00

cpu

inorder: dont allow early loads

2010-01-31 18:25:27 -05:00

dev

X86: Add a latency that describes how long an interrupt takes to propagate through the IO APIC.

2009-12-19 01:50:06 -08:00

doxygen

…

kern

SE: Fix SE mode OS X compilation.

2009-11-14 11:49:01 -06:00

mem

m5: Regression Tester Update

2010-01-29 20:29:40 -08:00

python

ply grammar: Fixup Tokenizer class so you can get lexer arguments

2009-09-23 18:28:29 -07:00

sim

util: do checkpoint aggregation more cleanly, fix last changeset.

2010-01-19 22:03:44 -08:00

unittest

includes: sort includes again

2009-05-17 14:34:52 -07:00

Doxyfile

…

SConscript

scons: deal with generated .py files properly

2009-11-08 17:35:49 -08:00