Gabe Black a73069c87d mem: Track the MemObject owner in MasterPort and SlavePort. ...

These types are much more tied to MemObjects and the gem5 memory
protocol than the Port or BaseMasterPort and BaseSlavePort classes.

Change-Id: I36bc8c75b9c74d28ee8b65dbcbf742cd41135742
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17032
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

2019-03-15 18:37:02 +00:00

..

arch

arch-arm,cpu: Add initial support for Arm SVE

2019-03-14 10:42:27 +00:00

base

base: Fix enums checkpointing

2019-02-18 09:57:33 +00:00

cpu

cpu: Refactor of Physical Register implementation

2019-03-14 15:09:07 +00:00

dev

dev: Make the EtherDevice class inherit EtherObject.

2019-03-15 18:13:46 +00:00

doc

docs: Fix power model doxygen

2018-04-20 15:59:35 +00:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

python: Don't assume SimObjects live in the global namespace

2019-02-12 09:43:00 +00:00

kern

kern,sim: implement FUTEX_WAKE_OP

2019-02-08 15:25:30 +00:00

learning_gem5

python: Don't assume SimObjects live in the global namespace

2019-02-12 09:43:00 +00:00

mem

mem: Track the MemObject owner in MasterPort and SlavePort.

2019-03-15 18:37:02 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

python: Simplify connectPorts() around EtherObject/EtherDevice.

2019-03-15 18:14:25 +00:00

sim

sim: Add size to array unserialization error message

2019-03-12 14:20:50 +00:00

systemc

tlm: Add some includes to some tlm_utils header files.

2019-03-01 23:40:52 +00:00

unittest

python: Replace dict.has_key with 'key in dict'

2019-02-12 17:36:12 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: Marshal Python sources using the same Python as gem5

2019-02-26 10:27:07 +00:00