This patches decouples the prefetchers from the cache implementation as the first step to allow using the classic prefetchers with ruby caches. The prefetchers that need do cache lookups can do so using the accessor object provided when the probes are notified. This may also facilitate connecting the same prefetcher to multiple caches. Related JIRA: https://gem5.atlassian.net/browse/GEM5-457 https://gem5.atlassian.net/browse/GEM5-1112 Change-Id: I4fee1a3613ae009fabf45d7b747e4582cad315ef Signed-off-by: Tiago Mück <tiago.muck@arm.com>
273 lines
9.8 KiB
C++
273 lines
9.8 KiB
C++
/*
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* Copyright (c) 2014-2015, 2023 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_CACHE_PREFETCH_QUEUED_HH__
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#define __MEM_CACHE_PREFETCH_QUEUED_HH__
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#include <cstdint>
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#include <list>
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#include <utility>
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#include "arch/generic/mmu.hh"
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#include "base/statistics.hh"
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#include "base/types.hh"
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#include "mem/cache/prefetch/base.hh"
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#include "mem/packet.hh"
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namespace gem5
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{
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struct QueuedPrefetcherParams;
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namespace prefetch
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{
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class Queued : public Base
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{
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protected:
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struct DeferredPacket : public BaseMMU::Translation
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{
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/** Owner of the packet */
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Queued *owner;
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/** Prefetch info corresponding to this packet */
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PrefetchInfo pfInfo;
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/** Time when this prefetch becomes ready */
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Tick tick;
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/** The memory packet generated by this prefetch */
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PacketPtr pkt;
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/** The priority of this prefetch */
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int32_t priority;
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/** Request used when a translation is needed */
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RequestPtr translationRequest;
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ThreadContext *tc;
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bool ongoingTranslation;
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const CacheAccessor *cache;
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/**
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* Constructor
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* @param o QueuedPrefetcher in charge of this request
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* @param pfi PrefechInfo object associated to this packet
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* @param t Time when this prefetch becomes ready
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* @param p PacketPtr with the memory request of the prefetch
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* @param prio This prefetch priority
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*/
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DeferredPacket(Queued *o, PrefetchInfo const &pfi, Tick t,
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int32_t prio, const CacheAccessor &_cache)
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: owner(o), pfInfo(pfi), tick(t), pkt(nullptr),
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priority(prio), translationRequest(), tc(nullptr),
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ongoingTranslation(false), cache(&_cache) {
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}
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bool operator>(const DeferredPacket& that) const
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{
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return priority > that.priority;
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}
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bool operator<(const DeferredPacket& that) const
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{
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return priority < that.priority;
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}
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bool operator<=(const DeferredPacket& that) const
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{
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return !(*this > that);
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}
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/**
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* Create the associated memory packet
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* @param paddr physical address of this packet
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* @param blk_size block size used by the prefetcher
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* @param requestor_id Requestor ID of the access that generated
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* this prefetch
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* @param tag_prefetch flag to indicate if the packet needs to be
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* tagged
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* @param t time when the prefetch becomes ready
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*/
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void createPkt(Addr paddr, unsigned blk_size, RequestorID requestor_id,
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bool tag_prefetch, Tick t);
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/**
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* Sets the translation request needed to obtain the physical address
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* of this request.
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* @param req The Request with the virtual address of this request
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*/
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void setTranslationRequest(const RequestPtr &req)
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{
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translationRequest = req;
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}
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void markDelayed() override
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{}
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void finish(const Fault &fault, const RequestPtr &req,
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ThreadContext *tc, BaseMMU::Mode mode) override;
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/**
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* Issues the translation request to the provided MMU
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* @param mmu the mmu that has to translate the address
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*/
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void startTranslation(BaseMMU *mmu);
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};
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std::list<DeferredPacket> pfq;
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std::list<DeferredPacket> pfqMissingTranslation;
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using const_iterator = std::list<DeferredPacket>::const_iterator;
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using iterator = std::list<DeferredPacket>::iterator;
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// PARAMETERS
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/** Maximum size of the prefetch queue */
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const unsigned queueSize;
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/**
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* Maximum size of the queue holding prefetch requests with missing
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* address translations
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*/
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const unsigned missingTranslationQueueSize;
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/** Cycles after generation when a prefetch can first be issued */
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const Cycles latency;
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/** Squash queued prefetch if demand access observed */
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const bool queueSquash;
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/** Filter prefetches if already queued */
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const bool queueFilter;
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/** Snoop the cache before generating prefetch (cheating basically) */
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const bool cacheSnoop;
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/** Tag prefetch with PC of generating access? */
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const bool tagPrefetch;
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/** Percentage of requests that can be throttled */
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const unsigned int throttleControlPct;
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struct QueuedStats : public statistics::Group
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{
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QueuedStats(statistics::Group *parent);
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// STATS
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statistics::Scalar pfIdentified;
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statistics::Scalar pfBufferHit;
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statistics::Scalar pfInCache;
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statistics::Scalar pfRemovedDemand;
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statistics::Scalar pfRemovedFull;
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statistics::Scalar pfSpanPage;
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statistics::Scalar pfUsefulSpanPage;
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} statsQueued;
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public:
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using AddrPriority = std::pair<Addr, int32_t>;
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Queued(const QueuedPrefetcherParams &p);
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virtual ~Queued();
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void
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notify(const CacheAccessProbeArg &acc, const PrefetchInfo &pfi) override;
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void insert(const PacketPtr &pkt, PrefetchInfo &new_pfi, int32_t priority,
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const CacheAccessor &cache);
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virtual void calculatePrefetch(const PrefetchInfo &pfi,
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std::vector<AddrPriority> &addresses,
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const CacheAccessor &cache) = 0;
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PacketPtr getPacket() override;
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Tick nextPrefetchReadyTime() const override
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{
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return pfq.empty() ? MaxTick : pfq.front().tick;
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}
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void printQueue(const std::list<DeferredPacket> &queue) const;
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private:
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/**
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* Adds a DeferredPacket to the specified queue
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* @param queue selected queue to use
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* @param dpp DeferredPacket to add
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*/
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void addToQueue(std::list<DeferredPacket> &queue, DeferredPacket &dpp);
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/**
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* Starts the translations of the queued prefetches with a
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* missing translation. It performs a maximum specified number of
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* translations. Successful translations cause the prefetch request to be
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* queued in the queue of ready requests.
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* @param max maximum number of translations to perform
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*/
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void processMissingTranslations(unsigned max);
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/**
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* Indicates that the translation of the address of the provided deferred
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* packet has been successfully completed, and it can be enqueued as a
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* new prefetch request.
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* @param dp the deferred packet that has completed the translation request
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* @param failed whether the translation was successful
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* @param cache accessor for lookups on the cache that originated this pkt
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*/
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void translationComplete(DeferredPacket *dp, bool failed,
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const CacheAccessor &cache);
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/**
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* Checks whether the specified prefetch request is already in the
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* specified queue. If the request is found, its priority is updated.
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* @param queue selected queue to check
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* @param pfi information of the prefetch request to be added
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* @param priority priority of the prefetch request to be added
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* @return True if the prefetch request was found in the queue
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*/
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bool alreadyInQueue(std::list<DeferredPacket> &queue,
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const PrefetchInfo &pfi, int32_t priority);
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/**
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* Returns the maxmimum number of prefetch requests that are allowed
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* to be created from the number of prefetch candidates provided.
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* The behavior of this service is controlled with the throttleControlPct
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* parameter.
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* @param total number of prefetch candidates generated by the prefetcher
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* @return the number of these request candidates are allowed to be created
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*/
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size_t getMaxPermittedPrefetches(size_t total) const;
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RequestPtr createPrefetchRequest(Addr addr, PrefetchInfo const &pfi,
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PacketPtr pkt);
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};
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} // namespace prefetch
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} // namespace gem5
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#endif //__MEM_CACHE_PREFETCH_QUEUED_HH__
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