Daniel R. Carvalho a5408244d1 mem-ruby: Remove shiftLowOrderBits ...

There is no need to encapsulate a shift operation.

Change-Id: Ie711d8d4975d1d9dde656cc2284a048410cfdadb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21083
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2019-09-30 20:58:46 +00:00

..

arch

fastmodel: Add glue code which adapts fastmodels to run in gem5.

2019-09-27 22:53:47 +00:00

base

stats: Add a preDumpStats() callback to Stats::Group

2019-09-26 10:05:03 +00:00

cpu

cpu: Make use of DRAMCtrl::AddrMap in the traffic generators

2019-09-30 20:36:30 +00:00

dev

x86: Templatize the IntMasterPort.

2019-09-21 05:05:18 +00:00

doc

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

doxygen

…

gpu-compute

gpu-compute: Fix overriden errors

2019-09-20 22:42:31 +00:00

kern

kern: Replace an explicitly instantiated port proxy with one from the tc.

2019-05-30 14:20:03 +00:00

learning_gem5

dev: Scrub out some lingering uses of MemObject.

2019-09-09 01:54:36 +00:00

mem

mem-ruby: Remove shiftLowOrderBits

2019-09-30 20:58:46 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

misc: Added line wrapping functionality for Sim-Object desc

2019-09-30 19:50:26 +00:00

sim

sim: Convert power modelling framework to new-style stats

2019-09-26 13:22:55 +00:00

systemc

systemc: Make TLM port wrappers for tlm_base_(target|initiator)_socket.

2019-09-17 19:07:59 +00:00

unittest

python: Replace dict.has_key with 'key in dict'

2019-02-12 17:36:12 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: Move the marshal binary to the build directory

2019-05-21 15:46:50 +00:00