5bce5673b0
A set of cpt_upgraders was patching old checkpoints regardless of the ISA in use. Thanks to the previous patch, we can now retrieve the ISA of the CPU from the isa section. Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: Ia110068c06453796cefac028ee13f21667e5371a Reviewed-by: Richard Cooper <richard.cooper@arm.com>
64 lines
2.9 KiB
Python
64 lines
2.9 KiB
Python
# Copyright (c) 2024 Arm Limited
|
|
# All rights reserved
|
|
#
|
|
# The license below extends only to copyright in the software and shall
|
|
# not be construed as granting a license to any other intellectual
|
|
# property including but not limited to intellectual property relating
|
|
# to a hardware implementation of the functionality of the software
|
|
# licensed hereunder. You may use the software subject to the license
|
|
# terms below provided that you ensure that this notice is replicated
|
|
# unmodified and in its entirety in all distributions of the software,
|
|
# modified or unmodified, in source code or in binary form.
|
|
#
|
|
# Copyright (c) 2023 Barcelona Supercomputing Center (BSC)
|
|
# All rights reserved.
|
|
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions are
|
|
# met: redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer;
|
|
# redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
# documentation and/or other materials provided with the distribution;
|
|
# neither the name of the copyright holders nor the names of its
|
|
# contributors may be used to endorse or promote products derived from
|
|
# this software without specific prior written permission.
|
|
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
|
|
def upgrader(cpt):
|
|
"""
|
|
Update the checkpoint to support initial RVV implemtation.
|
|
The updater is taking the following steps.
|
|
|
|
Set vector registers to occupy 327680 bytes (40regs * 8192bytes).
|
|
Vector registers now ocupy this space regardless of VLEN as the
|
|
VecRegContainer is always MaxVecLenInBytes.
|
|
"""
|
|
|
|
import re
|
|
|
|
for sec in cpt.sections():
|
|
# Search for all XC sections
|
|
|
|
res = re.search(r"(.*processor.*\.core.*)\.xc.*", sec)
|
|
if res and cpt.get(res.groups()[0] + ".isa", "isaName") == "riscv":
|
|
# Only update for RISCV XCs
|
|
# Updating RVV vector registers (dummy values)
|
|
mr = cpt.get(sec, "regs.vector").split()
|
|
if len(mr) != 327680:
|
|
cpt.set(
|
|
sec, "regs.vector", " ".join("0" for i in range(327680))
|
|
)
|