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According to the ArmArm: "When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted." Since ISTATUS is simply flagging that timer conditions are met, an interrupt mask (via the <timer>_CTL_EL<x>.IMASK) shouldn't reset the field to 0. Clearing the ISTATUS bit leads to the following problem as an example: 1) virtual timer (EL1) issuing a physical interrupt to the GIC 2) hypervisor handling the physical interrupt; setting the CNTV_CTL_EL0.IMASK to 1 before issuing the virtual interrupt to the VM 3) The VM receives the virtual interrupt but it gets confused since CNTV_CTL_EL0.ISTATUS is 0 (due to point 2) What happens when we disable the timer? "When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN." So we are allowed to not clear the ISTATUS bit if the timer gets disabled Change-Id: I8eb32459a3ef6829c1910cf63815e102e2705566 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Adrian Herrera <adrian.herrera@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31775 Reviewed-by: Hsuan Hsu <kugwa2000@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This is the gem5 simulator. The main website can be found at http://www.gem5.org A good starting point is http://www.gem5.org/about, and for more information about building the simulator and getting started please see http://www.gem5.org/documentation and http://www.gem5.org/documentation/learning_gem5/introduction. To build gem5, you will need the following software: g++ or clang, Python (gem5 links in the Python interpreter), SCons, SWIG, zlib, m4, and lastly protobuf if you want trace capture and playback support. Please see http://www.gem5.org/documentation/general_docs/building for more details concerning the minimum versions of the aforementioned tools. Once you have all dependencies resolved, type 'scons build/<ARCH>/gem5.opt' where ARCH is one of ARM, NULL, MIPS, POWER, SPARC, or X86. This will build an optimized version of the gem5 binary (gem5.opt) for the the specified architecture. See http://www.gem5.org/documentation/general_docs/building for more details and options. The basic source release includes these subdirectories: - configs: example simulation configuration scripts - ext: less-common external packages needed to build gem5 - src: source code of the gem5 simulator - system: source for some optional system software for simulated systems - tests: regression tests - util: useful utility programs and files To run full-system simulations, you will need compiled system firmware (console and PALcode for Alpha), kernel binaries and one or more disk images. If you have questions, please send mail to gem5-users@gem5.org Enjoy using gem5 and please share your modifications and extensions.