Gabe Black 9b1abd4d83 cpu: Use RegVal for VecElems instead of TheISA::VecElem. ...

If VecElem is a basic type, which is a reasonable assumption, it can be
contained in a RegVal. We still need to use the TheISA::VecElem type to
extract it from an actual vector, but then it can be passed around as a
RegVal.

Change-Id: I4dc470e7cc369499ce3686dd291eb3d93ca0819a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49124
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-08-11 04:48:02 +00:00

..

cpu_impl.hh

misc: Move Mode and Translation from BaseTLB to BaseMMU

2021-07-07 08:44:13 +00:00

cpu.cc

misc: Move Mode and Translation from BaseTLB to BaseMMU

2021-07-07 08:44:13 +00:00

cpu.hh

cpu: Use RegVal for VecElems instead of TheISA::VecElem.

2021-08-11 04:48:02 +00:00

SConsopts

scons: Turn the ISA and GPU ISA lists into construction variables.

2021-08-07 03:12:56 +00:00

thread_context.hh

cpu: Use RegVal for VecElems instead of TheISA::VecElem.

2021-08-11 04:48:02 +00:00