Ciro Santilli b5cc34d767 arch-arm: correctly set floats from GDB on aarch64 ...

aarch64 floating point registers are now stored as vector type, but this
was not updated in the stub.

Change-Id: I4a2bc1cea0eec9beeb5bbd49e2a868b9d5ed0a42
Reviewed-on: https://gem5-review.googlesource.com/c/14498
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

2018-12-03 10:43:15 +00:00

..

alpha

arch: Get rid of the unused type AnyReg.

2018-10-17 20:15:26 +00:00

arm

arch-arm: correctly set floats from GDB on aarch64

2018-12-03 10:43:15 +00:00

generic

arch: Include some additional headers in arch/generic/mmapped_ipr.cc.

2018-10-17 20:19:03 +00:00

hsail

hsail: Fix a warning/build failure for HSAIL_X86.

2018-11-27 22:02:50 +00:00

mips

arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

2018-11-27 21:58:24 +00:00

null

null: Claim to use 64 bit floating point registers.

2018-11-05 23:43:10 +00:00

power

arch: Get rid of the unused type AnyReg.

2018-10-17 20:15:26 +00:00

riscv

syscall_emul: expand AuxVector class

2018-09-19 20:51:17 +00:00

sparc

sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.

2018-11-05 23:42:51 +00:00

x86

sim-se: only implement getdentsFunc on supported hosts

2018-11-27 11:46:36 +00:00

isa_parser.py

arch, arm: Fix implicit-fallthrough GCC warnings

2018-03-20 20:17:00 +00:00

micro_asm_test.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

micro_asm.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

SConscript

arch: Remove the "arch/tlb.hh" switching header.

2018-01-23 20:39:24 +00:00