Anouk Van Laer 6684d617da dev, arm: Removed contextId variable ...

The contextId variable is only used by the debug flag and will prevent
a more optimised binary (i.e. fast) from compiling.

Change-Id: I6cefb5bc06d0d4b415df62f1278db53ba309fb87
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16042
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

2019-02-01 11:22:50 +00:00

..

alpha

alpha: Use little endian packet accessors.

2018-10-12 23:58:21 +00:00

arm

dev, arm: Removed contextId variable

2019-02-01 11:22:50 +00:00

i2c

dev: Explicitly specify the endianness for packet accessors.

2018-10-17 20:17:44 +00:00

mips

dev: Remove a bunch of Alpha code from MIPS, and unnecessary TheISAs.

2018-03-27 10:58:10 +00:00

net

dev: Explicitly specify the endianness for packet accessors.

2018-10-17 20:17:44 +00:00

pci

dev: Explicitly specify the endianness for packet accessors.

2018-10-17 20:17:44 +00:00

ps2

ps2: Unify constant names

2018-04-17 12:24:17 +00:00

serial

dev: Remove using namespace TheISA in uart8250.cc.

2018-10-17 20:18:29 +00:00

sparc

sparc: Use big endian packet accessors.

2018-10-12 23:47:36 +00:00

storage

dev: Explicitly specify the endianness for packet accessors.

2018-10-17 20:17:44 +00:00

virtio

dev: Explicitly specify the endianness for packet accessors.

2018-10-17 20:17:44 +00:00

x86

x86: Use little endian packet accessors.

2018-10-12 23:44:38 +00:00

baddev.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

baddev.hh

AddrRange: Transition from Range<T> to AddrRange

2012-09-19 06:15:44 -04:00

BadDevice.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

Device.py

arm: DT autogeneration - autogenerate RealView Platform devices

2018-01-29 22:22:23 +00:00

dma_device.cc

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

dma_device.hh

dev: Refactor some Event subclasses to lambdas

2017-07-12 20:07:05 +00:00

intel_8254_timer.cc

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

intel_8254_timer.hh

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

io_device.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

io_device.hh

sim: Decouple draining from the SimObject hierarchy

2015-07-07 09:51:05 +01:00

isa_fake.cc

dev: Explicitly specify the endianness for packet accessors.

2018-10-17 20:17:44 +00:00

isa_fake.hh

AddrRange: Transition from Range<T> to AddrRange

2012-09-19 06:15:44 -04:00

mc146818.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

mc146818.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

pixelpump.cc

dev: Add support for single-pass scan out in the PixelPump

2017-03-07 11:14:28 +00:00

pixelpump.hh

dev: Add support for single-pass scan out in the PixelPump

2017-03-07 11:14:28 +00:00

platform.cc

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

platform.hh

dev: Rewrite PCI host functionality

2015-12-05 00:11:24 +00:00

Platform.py

arm: DT autogeneration - Generate cpus node

2018-01-29 22:21:48 +00:00

rtcreg.h

dev: Clean up MC146818 register (A & B) handling

2013-06-03 12:28:41 +02:00

SConscript

dev: Include the platform base class even in NULL_ISA builds.

2018-10-12 23:39:14 +00:00