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sparc: Use big endian packet accessors.

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We know data is big endian, so we can use those accessors
explicitly.

Change-Id: I06fe35254433b20db05f5f10d0ca29a44d47c301
Reviewed-on: https://gem5-review.googlesource.com/c/13458
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2018-10-12 05:01:06 -07:00
parent 9125a43f62
commit cc33e2e349
4 changed files with 61 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

66
src/arch/sparc/tlb.cc
View File

@@ -871,90 +871,90 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
switch (asi) {
case ASI_LSU_CONTROL_REG:
assert(va == 0);
pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
pkt->setBE(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
break;
case ASI_MMU:
switch (va) {
case 0x8:
pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
pkt->setBE(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
break;
case 0x10:
pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
pkt->setBE(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
break;
default:
goto doMmuReadError;
}
break;
case ASI_QUEUE:
pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
pkt->setBE(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
(va >> 4) - 0x3c));
break;
case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
assert(va == 0);
pkt->set(c0_tsb_ps0);
pkt->setBE(c0_tsb_ps0);
break;
case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
assert(va == 0);
pkt->set(c0_tsb_ps1);
pkt->setBE(c0_tsb_ps1);
break;
case ASI_DMMU_CTXT_ZERO_CONFIG:
assert(va == 0);
pkt->set(c0_config);
pkt->setBE(c0_config);
break;
case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
assert(va == 0);
pkt->set(itb->c0_tsb_ps0);
pkt->setBE(itb->c0_tsb_ps0);
break;
case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
assert(va == 0);
pkt->set(itb->c0_tsb_ps1);
pkt->setBE(itb->c0_tsb_ps1);
break;
case ASI_IMMU_CTXT_ZERO_CONFIG:
assert(va == 0);
pkt->set(itb->c0_config);
pkt->setBE(itb->c0_config);
break;
case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
assert(va == 0);
pkt->set(cx_tsb_ps0);
pkt->setBE(cx_tsb_ps0);
break;
case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
assert(va == 0);
pkt->set(cx_tsb_ps1);
pkt->setBE(cx_tsb_ps1);
break;
case ASI_DMMU_CTXT_NONZERO_CONFIG:
assert(va == 0);
pkt->set(cx_config);
pkt->setBE(cx_config);
break;
case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
assert(va == 0);
pkt->set(itb->cx_tsb_ps0);
pkt->setBE(itb->cx_tsb_ps0);
break;
case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
assert(va == 0);
pkt->set(itb->cx_tsb_ps1);
pkt->setBE(itb->cx_tsb_ps1);
break;
case ASI_IMMU_CTXT_NONZERO_CONFIG:
assert(va == 0);
pkt->set(itb->cx_config);
pkt->setBE(itb->cx_config);
break;
case ASI_SPARC_ERROR_STATUS_REG:
pkt->set((uint64_t)0);
pkt->setBE((uint64_t)0);
break;
case ASI_HYP_SCRATCHPAD:
case ASI_SCRATCHPAD:
pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
pkt->setBE(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
break;
case ASI_IMMU:
switch (va) {
case 0x0:
temp = itb->tag_access;
pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
pkt->setBE(bits(temp,63,22) | bits(temp,12,0) << 48);
break;
case 0x18:
pkt->set(itb->sfsr);
pkt->setBE(itb->sfsr);
break;
case 0x30:
pkt->set(itb->tag_access);
pkt->setBE(itb->tag_access);
break;
default:
goto doMmuReadError;
@@ -964,26 +964,26 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
switch (va) {
case 0x0:
temp = tag_access;
pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
pkt->setBE(bits(temp,63,22) | bits(temp,12,0) << 48);
break;
case 0x18:
pkt->set(sfsr);
pkt->setBE(sfsr);
break;
case 0x20:
pkt->set(sfar);
pkt->setBE(sfar);
break;
case 0x30:
pkt->set(tag_access);
pkt->setBE(tag_access);
break;
case 0x80:
pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
pkt->setBE(tc->readMiscReg(MISCREG_MMU_PART_ID));
break;
default:
goto doMmuReadError;
}
break;
case ASI_DMMU_TSB_PS0_PTR_REG:
pkt->set(MakeTsbPtr(Ps0,
pkt->setBE(MakeTsbPtr(Ps0,
tag_access,
c0_tsb_ps0,
c0_config,
@@ -991,7 +991,7 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
cx_config));
break;
case ASI_DMMU_TSB_PS1_PTR_REG:
pkt->set(MakeTsbPtr(Ps1,
pkt->setBE(MakeTsbPtr(Ps1,
tag_access,
c0_tsb_ps1,
c0_config,
@@ -999,7 +999,7 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
cx_config));
break;
case ASI_IMMU_TSB_PS0_PTR_REG:
pkt->set(MakeTsbPtr(Ps0,
pkt->setBE(MakeTsbPtr(Ps0,
itb->tag_access,
itb->c0_tsb_ps0,
itb->c0_config,
@@ -1007,7 +1007,7 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
itb->cx_config));
break;
case ASI_IMMU_TSB_PS1_PTR_REG:
pkt->set(MakeTsbPtr(Ps1,
pkt->setBE(MakeTsbPtr(Ps1,
itb->tag_access,
itb->c0_tsb_ps1,
itb->c0_config,
@@ -1019,7 +1019,7 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
SparcISA::Interrupts * interrupts =
dynamic_cast<SparcISA::Interrupts *>(
tc->getCpuPtr()->getInterruptController(0));
pkt->set(interrupts->get_vec(IT_INT_VEC));
pkt->setBE(interrupts->get_vec(IT_INT_VEC));
}
break;
case ASI_SWVR_UDB_INTR_R:
@@ -1029,7 +1029,7 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
tc->getCpuPtr()->getInterruptController(0));
temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp);
pkt->set(temp);
pkt->setBE(temp);
}
break;
default:
@@ -1044,7 +1044,7 @@ doMmuReadError:
Cycles
TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
{
uint64_t data = pkt->get<uint64_t>();
uint64_t data = pkt->getBE<uint64_t>();
Addr va = pkt->getAddr();
ASI asi = (ASI)pkt->req->getArchFlags();

2
src/dev/sparc/dtod.cc
View File

@@ -64,7 +64,7 @@ DumbTOD::read(PacketPtr pkt)
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
assert(pkt->getSize() == 8);
pkt->set(todTime);
pkt->setBE(todTime);
todTime += 1000;
pkt->makeAtomicResponse();

30
src/dev/sparc/iob.cc
View File

@@ -96,7 +96,7 @@ Iob::readIob(PacketPtr pkt)
if (accessAddr < IntManAddr + IntManSize) {
int index = (accessAddr - IntManAddr) >> 3;
uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0;
pkt->set(data);
pkt->setBE(data);
return;
}
@@ -104,12 +104,12 @@ Iob::readIob(PacketPtr pkt)
int index = (accessAddr - IntCtlAddr) >> 3;
uint64_t data = intCtl[index].mask ? 1 << 2 : 0 |
intCtl[index].pend ? 1 << 0 : 0;
pkt->set(data);
pkt->setBE(data);
return;
}
if (accessAddr == JIntVecAddr) {
pkt->set(jIntVec);
pkt->setBE(jIntVec);
return;
}
@@ -129,23 +129,23 @@ Iob::readJBus(PacketPtr pkt)
if (accessAddr >= JIntData0Addr && accessAddr < JIntData1Addr) {
index = (accessAddr - JIntData0Addr) >> 3;
pkt->set(jBusData0[index]);
pkt->setBE(jBusData0[index]);
return;
}
if (accessAddr >= JIntData1Addr && accessAddr < JIntDataA0Addr) {
index = (accessAddr - JIntData1Addr) >> 3;
pkt->set(jBusData1[index]);
pkt->setBE(jBusData1[index]);
return;
}
if (accessAddr == JIntDataA0Addr) {
pkt->set(jBusData0[cpuid]);
pkt->setBE(jBusData0[cpuid]);
return;
}
if (accessAddr == JIntDataA1Addr) {
pkt->set(jBusData1[cpuid]);
pkt->setBE(jBusData1[cpuid]);
return;
}
@@ -153,13 +153,13 @@ Iob::readJBus(PacketPtr pkt)
index = (accessAddr - JIntBusyAddr) >> 3;
data = jIntBusy[index].busy ? 1 << 5 : 0 |
jIntBusy[index].source;
pkt->set(data);
pkt->setBE(data);
return;
}
if (accessAddr == JIntABusyAddr) {
data = jIntBusy[cpuid].busy ? 1 << 5 : 0 |
jIntBusy[cpuid].source;
pkt->set(data);
pkt->setBE(data);
return;
};
@@ -191,7 +191,7 @@ Iob::writeIob(PacketPtr pkt)
assert(IntManAddr == 0);
if (accessAddr < IntManAddr + IntManSize) {
index = (accessAddr - IntManAddr) >> 3;
data = pkt->get<uint64_t>();
data = pkt->getBE<uint64_t>();
intMan[index].cpu = bits(data,12,8);
intMan[index].vector = bits(data,5,0);
DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index,
@@ -201,7 +201,7 @@ Iob::writeIob(PacketPtr pkt)
if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
index = (accessAddr - IntCtlAddr) >> 3;
data = pkt->get<uint64_t>();
data = pkt->getBE<uint64_t>();
intCtl[index].mask = bits(data,2,2);
if (bits(data,1,1))
intCtl[index].pend = false;
@@ -211,7 +211,7 @@ Iob::writeIob(PacketPtr pkt)
}
if (accessAddr == JIntVecAddr) {
jIntVec = bits(pkt->get<uint64_t>(), 5,0);
jIntVec = bits(pkt->getBE<uint64_t>(), 5,0);
DPRINTF(Iob, "Wrote jIntVec %d\n", jIntVec);
return;
}
@@ -221,7 +221,7 @@ Iob::writeIob(PacketPtr pkt)
int cpu_id;
int vector;
index = (accessAddr - IntManAddr) >> 3;
data = pkt->get<uint64_t>();
data = pkt->getBE<uint64_t>();
type = (Type)bits(data,17,16);
cpu_id = bits(data, 12,8);
vector = bits(data,5,0);
@@ -242,14 +242,14 @@ Iob::writeJBus(PacketPtr pkt)
if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
index = (accessAddr - JIntBusyAddr) >> 3;
data = pkt->get<uint64_t>();
data = pkt->getBE<uint64_t>();
jIntBusy[index].busy = bits(data,5,5);
DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", index,
jIntBusy[index].busy);
return;
}
if (accessAddr == JIntABusyAddr) {
data = pkt->get<uint64_t>();
data = pkt->getBE<uint64_t>();
jIntBusy[cpuid].busy = bits(data,5,5);
DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", cpuid,
jIntBusy[cpuid].busy);

24
src/dev/sparc/mm_disk.cc
View File

@@ -83,23 +83,23 @@ MmDisk::read(PacketPtr pkt)
}
switch (pkt->getSize()) {
case sizeof(uint8_t):
pkt->set(diskData[accessAddr % SectorSize]);
DPRINTF(IdeDisk, "reading byte %#x value= %#x\n", accessAddr, diskData[accessAddr %
SectorSize]);
pkt->setRaw(diskData[accessAddr % SectorSize]);
DPRINTF(IdeDisk, "reading byte %#x value= %#x\n",
accessAddr, diskData[accessAddr % SectorSize]);
break;
case sizeof(uint16_t):
memcpy(&d16, diskData + (accessAddr % SectorSize), 2);
pkt->set(htobe(d16));
pkt->setRaw(d16);
DPRINTF(IdeDisk, "reading word %#x value= %#x\n", accessAddr, d16);
break;
case sizeof(uint32_t):
memcpy(&d32, diskData + (accessAddr % SectorSize), 4);
pkt->set(htobe(d32));
pkt->setRaw(d32);
DPRINTF(IdeDisk, "reading dword %#x value= %#x\n", accessAddr, d32);
break;
case sizeof(uint64_t):
memcpy(&d64, diskData + (accessAddr % SectorSize), 8);
pkt->set(htobe(d64));
pkt->setRaw(d64);
DPRINTF(IdeDisk, "reading qword %#x value= %#x\n", accessAddr, d64);
break;
default:
@@ -143,22 +143,22 @@ MmDisk::write(PacketPtr pkt)
switch (pkt->getSize()) {
case sizeof(uint8_t):
diskData[accessAddr % SectorSize] = htobe(pkt->get<uint8_t>());
DPRINTF(IdeDisk, "writing byte %#x value= %#x\n", accessAddr, diskData[accessAddr %
SectorSize]);
diskData[accessAddr % SectorSize] = htobe(pkt->getRaw<uint8_t>());
DPRINTF(IdeDisk, "writing byte %#x value= %#x\n",
accessAddr, diskData[accessAddr % SectorSize]);
break;
case sizeof(uint16_t):
d16 = htobe(pkt->get<uint16_t>());
d16 = pkt->getRaw<uint16_t>();
memcpy(diskData + (accessAddr % SectorSize), &d16, 2);
DPRINTF(IdeDisk, "writing word %#x value= %#x\n", accessAddr, d16);
break;
case sizeof(uint32_t):
d32 = htobe(pkt->get<uint32_t>());
d32 = pkt->getRaw<uint32_t>();
memcpy(diskData + (accessAddr % SectorSize), &d32, 4);
DPRINTF(IdeDisk, "writing dword %#x value= %#x\n", accessAddr, d32);
break;
case sizeof(uint64_t):
d64 = htobe(pkt->get<uint64_t>());
d64 = pkt->getRaw<uint64_t>();
memcpy(diskData + (accessAddr % SectorSize), &d64, 8);
DPRINTF(IdeDisk, "writing qword %#x value= %#x\n", accessAddr, d64);
break;